A decade ago, China relied heavily on foreign suppliers for high-end flash memory. Then a fab in Wuhan bet on a manufacturing approach that was relatively uncommon at the time. The result now sits inside consumer SSDs sold around the world.
That fab is YMTC (长江存储), or Yangtze Memory Technologies, and the trick is called Xtacking. It is less about piling more layers onto a single wafer and more about building two wafers and gluing them together. The approach has let a late-entrant Chinese memory maker reach the 232-layer class far faster than its chronological head start would suggest.
Key takeaways
- YMTC (长江存储), founded in Wuhan in 2016, reached 232-layer 3D NAND with its fourth-generation X3-9070 part, built on the Xtacking 3.0 architecture unveiled in August 2022 and in mass production by late that year.
- Xtacking bonds two separate wafers — a CMOS logic wafer and a memory-array wafer — face to face, instead of building one tall stack on a single wafer.
- The 232-layer TLC die ships 1 terabit (128 GB) per die and runs I/O up to 2,400 MT/s over the ONFI 5.0 interface.
- Hybrid bonding pulls the bonding-pad pitch down to about 0.8 µm, a figure a single teardown firm measured directly.
- US export controls introduced in October 2022, and YMTC's placement on the Entity List in December 2022, still cap the equipment the company can buy for 128-layer-and-above NAND.
Why bond two wafers instead of stacking one
Conventional 3D NAND is a single vertical tower: dozens or hundreds of word-line layers etched into one wafer, with the control logic buried at the base. The taller the tower, the harder the manufacturing. Yole SystemPlus, which physically decapped and imaged the chip, found YMTC split its 232 active word-lines into two decks rather than etching one monolithic stack. If built in a single deck, the channel aspect ratio would have reached roughly 109:1, a trench-etching and filling nightmare. Splitting it tamed that ratio and cut etch defects.
The more unusual move is the bonding. YMTC builds the memory array on one wafer and the peripheral CMOS logic on another, then joins them face to face using copper-to-copper hybrid direct bonding — no adhesive, no through-silicon vias in the usual sense. Both wafers can be made in parallel, shortening the production cycle when demand spikes. Yole measured a bonding-pad pitch as tight as 0.8 µm, and reported tight pad alignment without drawing a yield conclusion.
What the density actually bought
Density is the metric that matters for cost-per-bit. Yole reported the 232-layer die at 15.47 Gb/mm², above the roughly 10.9 and 10.29 Gb/mm² it quoted for Samsung's and Micron's 176-layer parts. A separate 232-layer QLC variant, found by TechInsights inside the ZhiTai Ti600 1 TB SSD in July 2023, reached 19.8 Gb/mm² — the first QLC die the firm had seen with more than 200 active word-lines in a shipping product. That is the real story: not just catching up on layer count, but matching or beating incumbent bit density while using a structurally different method.
The sanctions wall is the part the spec sheet hides
The technology narrative is clean; the business narrative is not. In October 2022 the US Department of Commerce restricted the licensing of 128-layer-and-above NAND equipment for use in China, and YMTC was added to the Entity List that December. Yole has noted the company still holds only a modest global market share and remains well behind Samsung, SK hynix, Micron, Western Digital and Kioxia in scale. The 2025–2026 memory upturn — TrendForce estimated NAND contract prices rose roughly 20–25% in 4Q25, 55–60% in 1Q26 and 70–75% in 2Q26 — has lifted the whole sector, but those figures are analyst estimates, not YMTC-specific results.
What readers can do now
- If you buy storage, know the product exists at retail. Xtacking-based SSDs such as the ZhiTai Ti600 are shipping; density claims are independently verified by teardown firms, not just vendor marketing.
- If you follow the supply chain, track hybrid bonding as a structural trend, not a one-off. Bonding two optimized wafers is becoming a way to add density without ever-taller, ever-harder single-stack etching.
- If you assess China's chip autonomy, watch equipment access, not layer count. The bottleneck for YMTC is the tools it can legally import, not its architecture.
Honest limitations
This article draws on Yole SystemPlus and TechInsights teardown reports, Reuters and PRNewswire launch coverage, and Global Times reporting. Density (15.47 Gb/mm²) and pad pitch (0.8 µm) come from single teardown firms and were not independently re-measured here. The NAND price trajectory is a TrendForce forward estimate and is flagged as such. Market-share context is Yole's qualitative assessment. I have not covered YMTC's newer Xtacking 4.0 generation in detail, and I have deliberately avoided implying the company leads the global NAND market — by volume it remains a challenger.