At a Beijing conference hall in late February, a row of demo boards sat quietly on a table — a laptop, a robot controller, a small server blade. None of them ran on the instruction sets that dominate global computing.
The chips inside carried a different DNA: an open, royalty-free architecture that a loose global community, not a single vendor, governs. For Alibaba's Damo Academy (达摩院), that architecture is now a strategic front.
The question is no longer whether RISC-V works. It is whether an open core can shoulder the server rooms and AI clusters that today depend on proprietary silicon.
Key takeaways
- XuanTie C930, a server-grade RISC-V core, began delivery in March 2025 with SPECint2006 of 15/GHz (Damo Academy, 2025 XuanTie conference).
- C930 pairs a 512-bit RVV1.0 vector unit with an 8 TOPS Matrix engine and supports 16 to 64 cores (Damo Academy).
- XuanTie reported over 4 billion cumulative shipped units as of early 2024; its site now lists 6 billion+ authorized units (Damo Academy / XuanTie official site).
- The team claims to have driven deployment of more than 30% of RISC-V high-performance processors (Damo Academy / Ni Guangnan).
- New roadmap parts include C908X (AI-dedicated, 4096-bit RVV), R908A (automotive) and XL200 (multi-cluster interconnect) (Damo Academy).
- RISC-V International approved 25 standards in 2024, over half tied to high-performance or AI use (RISC-V International, via China Daily).
From a martial-arts name to a server core
XuanTie (玄铁) is the RISC-V processor brand of Alibaba's Damo Academy (达摩院). The team was formed in 2018 by merging the academy's efforts with C-Sky (中天微), one of China's earliest RISC-V explorations. Since the first high-performance core, C910, appeared in 2019, the family has grown to four series and thirteen processors spanning low-power, real-time and high-performance tiers.
Crucially, XuanTie is an IP business, not a chip maker. It licenses processor cores and a software stack to downstream chip designers, who then build finished silicon. That licensing model is why shipment numbers are phrased in "authorized units" rather than branded boxes on a shelf.
What C930 actually is
At the 2025 XuanTie RISC-V Ecosystem Conference in late February, Damo Academy said its highest-performance core, C930, would begin delivery in March 2025. The company positioned it as its first server-grade CPU IP. The announced figures: a general-compute score of SPECint2006 15/GHz, a 512-bit RVV1.0 vector unit, and an 8 TOPS Matrix engine that binds general and AI compute in one block, with an open DSA extension interface (Damo Academy).
A senior technical expert at the academy, Li Chunqiang, described C930 as highly configurable, supporting designs from 16 to 64 cores for uses such as autonomous driving and network computing (NetEase / Global Times). Because it is an IP core, the real test is whether licensees turn it into competitive finished chips — and whether software, not just hardware, is ready.
The shipment base
XuanTie's credibility rests on volume. Damo Academy has reported more than 4 billion cumulative XuanTie-based chips shipped as of early 2024, across over 300 licensees (Damo Academy, via PCA / conference data). The XuanTie official site now lists 6 billion+ cumulative authorized units and 400+ partner customers. The gap between "shipped" and "authorized" matters: the larger figure counts licensed designs, not all in production, so the two should not be read as the same thing.
The team also says it has driven deployment of more than 30% of RISC-V high-performance processors in use — a claim attributed to academy leadership and academician Ni Guangnan at the conference. Treat that share as a self-reported estimate rather than an independently audited market figure.
Roadmap and the AI tilt
C930 is not the end of the story. Damo Academy disclosed a pipeline of new cores aimed at specific domains (Damo Academy):
- C908X: its first AI-dedicated processor, with a 4096-bit RVV1.0 vector width.
- R908A: an automotive-grade core built for high-reliability requirements.
- XL200: a larger multi-cluster coherent interconnect for scale-out designs.
Alongside the cores, the academy released three SDKs built on Linux, Android and RTOS, bundling virtualization, a confidential-computing framework and AI operator libraries.
The AI emphasis tracks a broader standards push. RISC-V International approved 25 standards in 2024, and more than half relate to high-performance or AI scenarios, according to foundation council chair Lu Dai, quoted at the event (China Daily). XuanTie's team holds leadership roles in the foundation's technical committees and is advancing a "Matrix" extension intended to make the open architecture a credible AI vehicle.
Why open cores matter now
For most of its life, RISC-V lived in microcontrollers and embedded devices. The move into server-grade and AI compute is the harder, more lucrative frontier — and the one where x86 and Arm are entrenched. An open instruction set gives buyers a third option and lets vendors customize accelerators without per-chip license fees.
According to Li An, chief scientist at BrainNet (脑机网), the interesting risk is not the core but the surrounding stack: an open ISA only pays off if compilers, operating systems and operator libraries mature fast enough to keep finished chips useful.
Honest limitations
This article relies on Damo Academy's own conference announcements and Chinese state and tech media; it does not independently benchmark C930. Performance figures such as SPECint2006 15/GHz and 8 TOPS are vendor-announced and unverified here. The shipment counts (4 billion shipped, 6 billion+ authorized) are company-reported and mix two different denominators. The claim of driving over 30% of RISC-V high-performance deployments is a self-reported estimate. RISC-V's readiness for large-scale AI training, as opposed to inference and edge, remains unproven at the time of writing.
What readers can do now
- Operators: pilot a XuanTie-based edge or inference board before assuming server-grade cores will drop into existing x86 workloads without porting effort.
- Investors: track whether C930 licensees ship finished, benchmarked silicon in 2026, not just IP announcements, as the real signal.
- Researchers: review the open RVV1.0 and Matrix extension proposals and test them against your own vector and inference kernels.