A chip rarely begins as a chip. Long before silicon is cut, a design house has already turned a customer's spec into register-transfer logic, picked the right blocks, and booked the foundry slot.
For VeriSilicon (芯原股份), that invisible work is the entire product. The Shanghai firm does not sell a branded processor; it sells the ability to assemble one from a catalog of owned building blocks.
The twist in 2025 was not a new block but a pile of orders — and the question of whether a design house can finally turn volume into profit.
Key takeaways
- VeriSilicon's 2025 revenue reached RMB 3.15B (US$444M; HK$3.47B), up 35.8% YoY, while net loss narrowed to RMB 528M (US$74M; HK$581M) (VeriSilicon 2025 annual report, SSE).
- Year-end backlog hit RMB 5.08B (US$715M; HK$5.58B), up 54% from Q3, with over 80% expected to convert within a year (VeriSilicon 2025 annual report).
- Mass-production service revenue rose 74% to RMB 1.49B (US$210M; HK$1.64B), becoming the largest segment at 47% of sales (VeriSilicon 2025 annual report).
- IP license fees reached RMB 671M (US$94.5M; HK$738M) and chip-design services RMB 877M (US$123M; HK$965M) (VeriSilicon 2025 annual report).
- Roughly 60% of the backlog is data-processing related, mainly cloud-side AI ASIC and IP orders (VeriSilicon 2025 annual report, via NetEase).
- The company continues to advance Chiplet (小芯片) technology and FD-SOI for IoT, per its annual report (VeriSilicon 2025 annual report).
A design house, not a chip maker
VeriSilicon is what the industry calls a silicon-platform company. It licenses its own semiconductor IP — processor cores, GPU and NPU blocks, image and video engines — and wraps that with one-stop chip customization and mass-production services. A customer that wants a custom chip but lacks a full design team can hand VeriSilicon a spec and receive a finished, fabricated part.
That model is different from a foundry, which only makes wafers, and from a chip vendor, which sells its own branded silicon. VeriSilicon sits in between: it owns the blocks and the design flow, but the end product carries the customer's name.
The 2025 numbers
The full-year results, filed with the Shanghai STAR Market on March 31, 2026, show a company growing fast but still in the red. Revenue reached RMB 3.152 billion (US$444 million; HK$3.47 billion), up 35.77% year on year. The net loss attributable to shareholders narrowed to RMB 528 million (US$74 million; HK$581 million) from RMB 601 million in 2024 — an improvement, but not a turn to profit (VeriSilicon 2025 annual report).
Margins compressed as the mix shifted. Gross margin was 34.19%, down 5.67 percentage points, and the company spent 42.78% of revenue on R&D. Operating cash flow improved to a negative RMB 222 million from negative RMB 346 million. Total assets jumped 66.7% to RMB 7.72 billion and net assets rose 61% to RMB 3.42 billion, a balance-sheet expansion that points to a sizeable capital raise during the year.
Where the revenue came from
The growth was not evenly spread. By segment (VeriSilicon 2025 annual report):
- Mass-production services — turning designs into shipped chips — rose 73.98% to RMB 1.49 billion (US$210 million; HK$1.64 billion) and became the largest segment at 47.25% of revenue.
- Chip-design services added RMB 877 million (US$123 million; HK$965 million), up 20.94%.
- IP license fees contributed RMB 671 million (US$94.5 million; HK$738 million), up a slower 6.07%.
The shift matters. A design house that only licenses IP earns high-margin, low-volume fees. One that also runs mass production can scale revenue far higher — but at lower margins and with more working capital tied up in inventory and foundry commitments. VeriSilicon is clearly leaning into the volume end of the business.
The backlog signal
The most telling figure is the order book. VeriSilicon ended 2025 with backlog of RMB 5.075 billion (US$715 million; HK$5.58 billion), up 54.45% from RMB 3.286 billion at the end of the third quarter, and the company said it had stayed high for nine straight quarters. More than 80% of that backlog is expected to convert to revenue within a year (VeriSilicon 2025 annual report).
About 60% of the backlog is tied to data processing, the company said, and most of that comes from cloud-side AI ASIC and IP work (NetEase, citing the annual report). In plain terms: customers building custom accelerators for data centers are handing VeriSilicon both the design and the production run. That is a different kind of demand than the company's traditional consumer-electronics and IoT base.
Chiplet and the longer game
Beyond the current order wave, VeriSilicon is pushing Chiplet (小芯片) technology and its industrialization, and using FD-SOI process for IoT products, according to its annual report. The logic is strategic: as monolithic scaling gets harder and more expensive, stitching licensed IP blocks into a single package is a natural fit for a company whose main asset is a broad IP catalog.
But "advancing" is not "shipping at scale." Heterogeneous integration remains early in commercialization, and VeriSilicon's own results show the near-term story is carried by ASIC and mass-production orders, not yet by a Chiplet platform revenue line.
Honest limitations
This article draws on VeriSilicon's 2025 annual report filed with the Shanghai STAR Market, corroborated by China Securities Journal and Sina Finance; the figures were not independently audited here. The company remains loss-making — the 2025 net loss of RMB 528 million narrowed but did not reverse, and gross margin fell 5.67 points as the lower-margin production mix grew. Backlog is an order book, not recognized revenue, and its conversion depends on customer tape-outs and foundry capacity. The "60% data-processing / cloud-AI ASIC" characterization of the backlog is the company's own. Currency figures use fixed rates of ¥7.1 = US$1 and ¥1 = HK$1.1.
What readers can do now
- Operators: if building a custom AI ASIC, evaluate VeriSilicon's IP catalog and turnkey flow as an alternative to in-house design, but price in mass-production lead times.
- Investors: track backlog conversion and gross-margin trajectory quarter by quarter; the loss-narrowing is real but the path to net profit is unproven.
- Researchers: follow VeriSilicon's Chiplet (小芯片) and FD-SOI disclosures as a signal for heterogeneous-integration adoption in China.