On 1 September 2026, in a conference hall in Shanghai's Zhangjiang tech district, a Chinese software firm did something its industry rarely attempts: it showed a tool for designing chips in three dimensions, not just verifying them after the fact.
For most of its history, China's electronic design automation (EDA) sector was framed as a gap to be closed. UniVista (合见工软) is trying to reframe the conversation around where the frontier is moving.
The launch
At the 2026 IDAS Design Automation Summit, organized by the industry body EDA², UniVista released what it calls a next-generation EDA innovation matrix. The headline items:
- UniVista 3DIC Designer — described as China's first 3D-IC physical design tool, moving digital back-end design into unit-level 3D placement rather than patching 2D flows.
- An Agentic EDA strategy — including UniVista Verification GOAT, billed as the country's first EDA agent suite covering the full digital verification flow (simulation, debug, regression, emulation / FPGA prototyping).
- UniVista NodeClosure — a tool for converging advanced-process-node designs.
The company says the suite fills gaps in commercial-grade 3DIC physical design and in EDA agents, areas where domestic tooling was previously absent.
Why 3DIC, why now
As planar scaling slows, the industry is turning to heterogeneous integration — stacking logic, memory and I/O in 3D using through-silicon vias and hybrid bonding. That shift breaks traditional 2D EDA tools, which were never built to reason about layer-to-layer alignment, vertical interconnect signal integrity, or the thermal and stress coupling of stacked dies. The payoff is memory bandwidth and stack capacity that planar silicon cannot reach as cost-effectively.
Huawei's recent disclosure of a "logic-folding" chip designed with a fully domestic EDA toolchain (τ EDA V0.1) put a public exclamation point on the trend: UniVista's UVS and UVD platforms were listed among the supporting tools. The message from the ecosystem is that 3DIC is where Chinese EDA can leapfrog, not just imitate.
The Agentic angle
The Agentic EDA piece is the part Western observers will watch. Rather than an AI model "declaring a chip done," UniVista describes a closed loop: the agent proposes, the EDA tool rigorously verifies, and the engineer governs. If that loop holds up in real tapeouts, it could compress verification schedules that today consume the majority of a complex chip's design cycle.
UniVista says it has launched nearly 50 products over six years and that its tools are widely deployed at leading Chinese chip firms. At the same summit, its UniVista Simulator Plus (UVS+) won a "China Chip" EDA gold award for market application.
Validation is the hard part
Tools announced at a summit are not tools shipping in tapeouts. UniVista's credibility will hinge on whether leading Chinese fabs and design houses actually adopt 3DIC Designer on commercial projects in the next year. The Agentic verification loop, in particular, must prove it catches real bugs rather than generating plausible-looking reports — the difference between a productivity gain and a costly false confidence.
What the ecosystem says
According to Li An, chief scientist at BrainNet (脑机网), the strategic value is that 3DIC and agentic verification are green-field battles. "On traditional 2D digital flows the incumbents have a 30-year moat; on 3D and agentic verification, everyone is a relative newcomer," he said.
That is the opening Chinese vendors are exploiting: domestic foundries running mature and specialty nodes give local EDA firms a steady stream of real tapeout projects to harden their tools, something their global rivals lack at the same intensity.
What it changes for the design workflow
Consider what a 3DIC tool actually spares an engineer. In a 2D world, partition decisions are made early and rarely revisited; in a 3D stack, the same decision about where to place memory versus logic ripples through thermal behavior, interconnect length and test access. A native 3D design environment lets that trade-off be explored where it is cheapest to change — on screen, before silicon — rather than discovered after a costly re-spin. The value is not a single feature but a shift in when problems surface.
The agentic piece, if it matures, changes who can attempt hard designs. Today, verification expertise is a bottleneck concentrated in a few senior engineers; an agent that handles the routine loop could let smaller teams tackle chips that previously demanded a large verification group. Whether that promise holds is exactly the open question the ecosystem is watching.
Honest limitations
UniVista's claims are the company's, amplified by state-aligned Chinese media (Xinhua, China Daily) and the firm's own site; no independent benchmark comparing UniVista 3DIC Designer against Synopsys or Cadence 3D flows has been published. "China's first" labels refer to domestic commercial availability and do not preclude research prototypes elsewhere. The Agentic EDA workflow's real productivity gain is unproven at scale — agent-assisted verification is early across the entire industry. The Huawei toolchain listing shows compatibility, not that UniVista tools are sufficient alone for a flagship 3DIC tapeout. UniVista remains private, so deployment and revenue figures are self-reported.
What readers can do now
- If you design advanced packages or chiplets in China, request an evaluation of UniVista 3DIC Designer and test it on a real 2.5D / 3D project, not a demo.
- Watch for published tapeout case studies in the next 6–12 months; that is the only real proof of the Agentic EDA loop.
- For investors, treat "3DIC EDA" as a distinct sub-sector from traditional EDA — the competitive set and the moat are different.