For three years the bottleneck hiding inside every Chinese AI accelerator was not the logic chip. It was the memory stacked beside it — the HBM (高带宽内存) that the country could not yet make.
ChangXin Memory (CXMT, 长鑫存储) is trying to change that before 2026 ends.
Key takeaways
- CXMT has delivered HBM3 (第三代高带宽内存) samples built on a 16nm process to Huawei and other domestic customers, with full mass production targeted for 2026.
- The company broke into 12-layer HBM stacking — a capability it reached roughly three years after entering the field in 2023.
- Trendforce projects CXMT's total DRAM capacity at 280,000 wafers/month in 2025, rising to 290,000–300,000 in 2026, with global DRAM share near 15% and revenue growth above 60%.
- CXMT's holding entity priced its STAR Market IPO at RMB 8.66/share in July 2026, raising about RMB 57.9 billion (≈ US$8.2 billion / HK$63 billion), the exchange's largest-ever listing.
The memory that AI cannot run without
An AI accelerator is only as fast as the data it can feed its compute dies. HBM (高带宽内存) — vertically stacked DRAM bonded close to the logic chip — supplies that bandwidth, and today it is made almost entirely by SK Hynix, Samsung, and Micron. For Chinese chipmakers blocked from buying the newest parts, no domestic HBM (高带宽内存) meant no complete domestic accelerator.
CXMT's answer is to redirect a slice of its DRAM capacity into HBM (高带宽内存). Reports say it is committing roughly 20% of DRAM output to HBM lines, which could yield HBM wafer capacity around 60,000 wafers/month once converted — enough to matter, though still a fraction of Korean volume.
From DDR5 to HBM in one stride
CXMT is not starting from zero. It mass-produced DDR5 DRAM on a 16nm (D1z) node in 2024, hitting 6400 Mbps, and by the second half of 2025 its DDR5 yield reportedly passed 80% — near mainstream spec. That process maturity is what it carried into HBM (高带宽内存).
The harder problems are vertical: bonding DRAM layers precisely, managing heat in a 12-high stack, and hitting yield on structures no Chinese fab had built before. CXMT entered HBM work in 2023 and, by reports, achieved a 12-layer stacking breakthrough using etching and packaging equipment co-developed with domestic toolmakers NAURA (北方华创) and AMEC (中微公司), since US restrictions block EUV and much advanced gear. Its gap to the Korean leaders, once about four years, is now described as under three.
The IPO that signals scale
In July 2026, CXMT's holding company opened STAR Market subscriptions at RMB 8.66/share, raising about RMB 57.9 billion before any greenshoe — and up to RMB 66.6 billion (≈ US$9.4 billion) if the over-allotment option is exercised. That tops the RMB 53.23 billion SMIC raised in 2020 and would be the largest IPO in the board's history. The original filing targeted RMB 29.5 billion; the final haul nearly doubled.
The money is earmarked for HBM (高带宽内存) fabs and DRAM upgrades. A Shanghai backend-packaging plant for HBM is scheduled to open by end-2026, and HBM3E development is targeted for 2027. The capital lets CXMT build the bonding and thermal infrastructure that memory leadership now requires.
The global HBM squeeze
HBM (高带宽内存) has become the single most supply-constrained component in AI hardware. Even SK Hynix and Samsung cannot meet demand, and allocations to Chinese customers have been restricted by export rules. That scarcity is exactly why a domestic source changes the equation so sharply. Memory is roughly a third of an AI server's bill of materials, and its price has climbed with every new accelerator generation. A Chinese HBM supply does not merely add resilience — it attacks the most inflated line item in the entire stack, and it removes the one component that, until now, no domestic accelerator could ship without.
Why this matters beyond China
HBM (高带宽内存) is the clearest single chokepoint in global AI hardware, and until now China had no seat at the table. A domestic HBM supply changes the calculus for every Chinese accelerator maker — Huawei, Cambricon, Hygon (海光) — by removing the most import-dependent component. For outside observers, it means the "China cannot build AI chips" narrative needs updating: the logic is largely there; the memory is now arriving. The remaining question is cost and yield at scale, where Korea still leads.
Honest limitations
CXMT's HBM3 is at sampling and early-mass-production stage, not the volume, cost-competitive position of SK Hynix's HBM3E or Samsung's latest. Yields on 12-layer stacks are reported lower than Korean rivals, and a 60,000-wafers/month HBM target depends on capacity conversion that has not fully happened. The "under three years behind" gap is an analyst characterization, not a benchmarked figure, and HBM4/16-layer work is still ahead. IPO figures are from the company's pricing disclosure; capacity and share numbers are Trendforce estimates.
What readers can do now
- Watch for CXMT's first commercial HBM3 shipment volume in 2026 — samples proved the process; volume proves the business.
- Track HBM3E development timing; catching the current generation matters less than narrowing the next one.
- Follow NAURA (北方华创) and AMEC (中微公司) equipment wins, since domestic HBM (高带宽内存) scale hinges on home-grown bonding and etching tools.