A smartphone chip shipped in late 2025 with almost no specifications attached. Huawei said nothing about the process, the factory or the node. That silence was the clue: the less said, the less Washington has to react to.
When analysts finally opened the Kirin 9030 inside the Mate 80 Pro Max, they confirmed what many suspected. The chip was built on Semiconductor Manufacturing International Corporation's (SMIC) N+3 process, a deep-ultraviolet (深紫外, DUV) achievement that proves China can push old machines further than anyone expected — and also how far it still sits from the frontier.
Key takeaways
- TechInsights identified the Kirin 9030 as an SMIC N+3 part, confirming volume production of a 5nm-class node without EUV lithography.
- SemiAnalysis measured N+3's minimum metal pitch at about 32.5 nm and its logic density at roughly 113 million transistors per square millimeter.
- That density sits near TSMC's N6 node (about 108 MTr/mm²), not TSMC's N5 or N3 families, which run far denser.
- SMIC reaches these figures through self-aligned quadruple patterning (自对准四重图形化, SAQP) and design-technology co-optimization, repeating DUV exposures many times.
- Analysts estimate N+3 yield near 30 percent versus over 90 percent on mature TSMC 5nm, with per-wafer cost roughly 50 percent higher.
What the teardown found
TechInsights, a Canadian firm known for physical reverse-engineering, confirmed the N+3 process and described it as a scaled evolution of SMIC's 7nm-class technology rather than a genuine 5nm node. SemiAnalysis later published its own teardown with harder numbers: a 32.5 nm tightest metal pitch and about 113 MTr/mm². For context, that is slightly above TSMC's N6 at roughly 108 MTr/mm², but well below TSMC's N3P at about 224 MTr/mm² and Intel 18A at about 238 MTr/mm².
The headline that "China beat Intel's pitch" is misleading on its own. A tighter wire pitch is one metric; density is the one that counts, and on density N+3 lands around a TSMC N6 equivalent. Calling it 5nm-class describes ambition and marketing, not the actual transistor budget.
How they did it without EUV
The trick is repetition. With no access to ASML's EUV scanners, SMIC prints critical layers using self-aligned quadruple patterning, running the same DUV exposure and etch sequence up to four times to squeeze features closer together. Combined with clever standard-cell design — fin depopulation, contact-over-active-gate structures and tight floorplanning — the effective density rises.
The cost is brutal. Every extra patterning step adds masks, cycle time and chances for a defect. Multi-patterning is why yields sit near 30 percent and why a finished wafer can cost about 50 percent more than a TSMC equivalent. The physics tax of skipping EUV is paid in volume and money.
The performance picture
Produced on N+3, the Kirin 9030 still posted real gains over its predecessor — more CPU cores and a meaningful GPU jump — and it was the first phone chip to add hardware ray tracing, by Huawei's account. But SemiAnalysis placed its top CPU core well behind Apple's 2020 M1 and its GPU behind the latest Qualcomm and MediaTek flagships by a wide margin. The process is a credibility milestone, not a performance lead.
For AI, the implication is the same as for phones. SMIC can make advanced-ish chips at home, but doing so at scale, yield and cost parity with TSMC remains out of reach. That is why Huawei's answer is supernodes and clusters rather than a single hero chip.
The foundry context
SMIC's N+3 is not an isolated feat. It is the manufacturing backbone behind Huawei's Ascend accelerators and a growing list of domestic AI chips, which is why its yield and cost directly shape how many Chinese AI systems can actually ship. A node that is real but expensive is still a strategic lifeline when the alternative is no advanced silicon at all, and the teardown is the only honest way to price that lifeline.
Why the silence
Huawei's habit of shipping spec-less flagships is rational. Each time a Chinese chip surprises Washington, a new restriction tends to follow. Saying less buys time. The teardowns, done independently, are how the outside world learns what was actually achieved — and, just as often, what was overstated.
Honest limitations
The density, pitch and yield figures here come from TechInsights and SemiAnalysis teardowns reported through secondary outlets; this review did not read the original paid reports, so the numbers should be treated as widely cited analyst measurements rather than primary data. Yield and cost-premium estimates originate from securities-research notes (for example Kiwoom) and are therefore indicative. The Kirin 9030's own performance claims are Huawei's and require independent verification. Process-node naming is SMIC's internal label and does not map one-to-one onto TSMC or Samsung nodes.
What readers can do now
- When you see "China achieves 5nm," check the density number (MTr/mm²), not the marketing node name — that is the honest comparison.
- For AI infrastructure, read SMIC N+3 as a strategic capability, not a substitute for frontier fabrication at scale.
- Follow TechInsights and SemiAnalysis teardowns as the most reliable public evidence of what Chinese fabs can actually ship.