A data-center operator in China this year faced a familiar puzzle: plenty of demand for AI training, but no easy way to scale the number of accelerators fast enough. The constraint was not ideas. It was silicon, and the schedule to deliver it.
At Huawei Connect 2025 in Shanghai, Rotating Chairman Xu Zhijun (徐直军) laid out a three-year roadmap that reframes how China's largest tech company plans to close its compute gap. The headline chip is Ascend 950 (昇腾950), the first in a series meant to ship on a near-annual rhythm.
Key takeaways
- Huawei announced the Ascend 950, 960 and 970 families at Huawei Connect 2025, with the 950PR targeted for the first quarter of 2026 and the 950DT for the fourth quarter of 2026.
- The 950PR is a prefill-optimized accelerator built for large-model inference, with official specs of up to 128 GB of memory and 1.6 TB/s of bandwidth.
- Huawei is pairing chips with "supernodes" (超节点) — racks of thousands of accelerators treated as one machine — to compensate for single-chip process limits.
- The strategy depends on a one-generation-per-year cadence, with Huawei stating it aims for roughly doubling compute each year through 2028.
- The 950PR supports low-precision formats including FP8, MXFP4 and Huawei's own HiF8, reflecting where inference economics are moving.
What the 950PR actually is
The Ascend 950 family splits into two chips with different jobs. The 950PR is tuned for the prefill stage of large-language-model serving, where batches of prompts are processed before tokens stream out. The 950DT, planned for later in 2026, is aimed at the decode and training side. Huawei's own Ascend community lists the 950PR with up to 1784 TFLOPS of MXFP4 compute, 128 GB of on-package memory and 1.6 TB/s of memory bandwidth, alongside support for FP8, MXFP8, FP4 and HiF8 (a Huawei format meant to keep FP8 efficiency with near-FP16 precision).
That memory figure matters. Modern inference lives or dies on how much model weight fits close to the compute, and 128 GB is enough to hold a sizeable model on a single card without aggressive sharding. The SIMD-plus-SIMT hybrid programming model is Huawei's attempt to make the chip feel less exotic to developers used to GPUs, letting the same hardware flow large contiguous vectors and fragmented irregular data.
Supernodes instead of single-chip heroics
The more interesting story is not the chip alone but how Huawei packages it. At the same event, Xu described Atlas 950 SuperPoD (超节点) clusters reaching 8192 Ascend cards and 8 EFLOPS of FP8 compute, with plans toward even larger clusters. The pitch is that, because the most advanced manufacturing nodes are out of reach, the right move is to wire many capable chips into one logical machine with low-latency optical interconnects.
The interconnect, branded Lingqu (灵衢) 2.0, is quoted by Huawei at up to 2 TB/s of bidirectional bandwidth per chip and is designed to keep thousands of accelerators working as a single pool. Whether that translates cleanly into real-world training efficiency depends on software, cooling and yield — none of which a spec sheet captures. The bet is that system-level scale can substitute for per-chip leadership.
Why a yearly cadence
Huawei's stated plan is one new Ascend family per year: 950 in 2026, 960 in 2027, 970 in 2028. The logic is that steady, predictable iterations beat waiting for a single breakthrough node. For Chinese AI labs blocked from buying the newest Nvidia parts, a dependable domestic cadence is itself a strategic asset, even if per-chip performance trails the frontier.
This is a systems bet. It trades elegance for availability, and it assumes Huawei can keep the software stack — CANN and the surrounding tooling — mature enough that buyers do not stall on porting. A fast chip with a thin ecosystem is just an expensive paperweight.
The competitive read
Nvidia still leads on raw per-chip performance and, more importantly, on the CUDA ecosystem that decades of developers trust. Huawei is not trying to win that comparison chip-for-chip. It is building a parallel stack with its own interconnect, compiler and cluster story, betting that sovereign demand inside China is large enough to fund the climb.
The risk is fragmentation. If every Chinese accelerator vendor builds its own software island, the domestic market fragments and none reaches the scale needed to challenge the incumbent. Huawei's decision to open the Lingqu 2.0 specification is a signal it wants the ecosystem to coalesce around its interconnect rather than splinter.
Honest limitations
This article relies on Huawei's own announcements at Huawei Connect 2025 and the company's Ascend product page; independent benchmark data for the 950PR in production is thin. The 950DT specs circulating in secondary sources are not confirmed by a primary document in this review and are therefore omitted. The supernode performance claims are Huawei's figures, not third-party measurements. Export-control and yield effects on real deployment volume are not quantified in public sources, and the comparison to Nvidia reflects stated positioning rather than head-to-head testing.
What readers can do now
- If you build or buy AI infrastructure in China, treat Ascend as a systems purchase: evaluate the whole supernode (超节点), not just the per-card spec sheet.
- For developers, start prototyping on CANN-compatible paths now; software maturity, not raw FLOPS, is the likely bottleneck.
- Track the 950DT's late-2026 arrival and third-party benchmarks before committing large training workloads to the family.