The rear panel comes off and the cabling is what you see first: hundreds of short, thick runs, dressed in bundles from one accelerator tray to the next. A technician works along the row with a torque driver. The rack is fully populated and doing nothing at all, because the links are not yet dressed and tested.
China's answer to a chip it cannot buy has turned into a bigger box. And the box is mostly wire.
Which is why the least glamorous documents this autumn matter more than most launches.
Key takeaways
- MIIT put China's intelligent compute (智算) at 2,592 EFLOPS at the end of September 2026, up 146% year on year (MIIT, 20 October 2026).
- The China Electronic Components Association published two high-speed copper-cable standards on 29 October 2026, both capped at 60 GHz and effective 1 November (CECA, Announcement No. 47 of 2026).
- The external-cable standard carries a 448 Gb/s per-lane reference at 110 GHz; the internal one covers 85, 92 and 100-ohm impedance (CECA).
- An industry consortium released a connector specification for near-packaged optics at its Shenzhen conference in October 2026, holding the electrical path to 20–150 mm (GCC).
- The eight-ministry AI+Manufacturing plan of 25 December 2025 names high-speed interconnect (高速互联) among the technologies to be broken through (MIIT).
The unit got bigger because the die did not
The Council on Foreign Relations estimates the best US AI chips at about five times Huawei's best on total processing performance, widening toward 17 times in the second half of 2027, and in its most Huawei-favourable scenario puts the company at roughly 5% of Nvidia's aggregate AI compute in 2025, falling toward 2% by 2027 (CFR, 2026).
One answer is to stop competing per chip and compete per domain: pack more accelerators into a single rack-scale unit (超节点, supernode) and connect them tightly enough that a training job treats the whole thing as one machine. If the processor is behind, make the cluster the product.
MIIT counted 2,592 EFLOPS of intelligent compute at the end of September 2026, 146% above a year earlier (MIIT, 20 October 2026). That number measures installed capacity, not how much of it sits inside one interconnected domain, and that gap is where the engineering has moved.
The wire decides the domain
The physics is unforgiving: raise the per-lane rate and usable copper length falls; switch to optics and you pay in power and cost per link. So the industry splits the job: copper inside the rack, optics between racks, and increasingly optics inside the package itself.
Near-packaged optics (NPO) puts the optical engine next to the switch or accelerator, which shortens the electrical path to the 20–150 mm range and removes the digital signal processor from the module. The Open AI Infra community, a grouping inside the Global Computing Consortium, published version 0.8 of a connector specification for those modules at the consortium's Shenzhen conference in October 2026. It fixes dimensions, footprint, pin assignment and power conditions for the optical-engine interface, and the group says the architecture is meant to carry 512-card and 1,024-card scale-up domains (GCC, October 2026).
Copper got its own paperwork that month. On 29 October the China Electronic Components Association approved two group standards for parallel symmetric cable: T/CECA 125—2026 for links inside servers and switches, T/CECA 126—2026 for links between them. Both take effect on 1 November 2026, both specify a 60 GHz maximum operating frequency, and the external standard adds a 448 Gb/s per-lane reference point at 110 GHz. Jiaxing Haitang Electronics led the internal-cable drafting; Zhejiang Zhaolong Interconnect led the external-cable work.
The purpose such a standard serves is plain: unify selection, testing and adaptation so that parts from different suppliers fit.
Group standards are not regulation
A 团体标准 (group standard) is written by an association and adopted voluntarily, and the distinction matters for anyone reading Chinese industrial policy. It is not a national standard, no regulator grants market access on it, and a supplier can ignore it. What it gives buyers is a shared vocabulary and a test method.
The state names the target rather than writing the clause. The eight-ministry AI+Manufacturing plan, issued as 工信部联科〔2025〕279号 on 25 December 2025 and published on 7 January 2026, lists high-speed interconnect among the technologies to be broken through, alongside high-end training chips and intelligent-compute cloud operating systems.
The detail lands at consortium level. The Global Computing Consortium says it has more than 500 members and over 40 standards and specifications; in October it released nine, including the connector specification, an 800V-to-50V power distribution design, a data format called HiFloat8 and requirements for confidential-computing data spaces (GCC).
What an interface does not settle
- A shared plug is not a shared fabric. Two vendors can agree on a connector and still run incompatible protocols above it; proprietary scale-up links remain the reference design at the top end.
- Version 0.8 is a draft. Publication means the interface is written down and downloadable, not that silicon built to it ships in volume.
- Volume is a manufacturing question. 1,024 accelerators in one domain is an assembly and field-service problem before it is a bandwidth problem.
- Standards do not buy wafers. Nothing here relaxes a lithography constraint; it changes how much system a given set of dies can become.
Honest limitations
Both are voluntary, and neither body publishes adoption counts, so nothing here shows how many racks use these interfaces. The consortium's members include companies that would benefit from its specifications, and its scale-up figures are design targets, not measured deployments. The 2,592 EFLOPS figure is an official aggregate with no published method for separating interconnected capacity from idle capacity. No shipment, yield or price data for NPO modules has been disclosed; the specification is pre-1.0.
What readers can do now
- When a vendor quotes a supernode size, ask for the link technology, the protocol above it, and whether that protocol is proprietary. A card count alone is marketing.
- Check the standard number in any pitch. A T/CECA citation is a voluntary group standard, a consortium specification weaker still; a GB or GB/T citation is national. They carry different weight in procurement and certification.
- Track revision history rather than launches — version 0.8 to 1.0 for the connector specification, and the next CECA cable revision. Interface definitions are where multi-vendor supply starts.