For two decades the easiest way to make a chip faster was to print smaller transistors. That path is getting brutally expensive — TSMC's 3nm wafers already run about US$20,000 each, and 2nm is expected to cost roughly 50% more. The semiconductor industry's answer is to stop shrinking and start stacking, and China's largest packaging house is betting it can do the stacking itself.
JCET (长电科技, 600584.SH) is the country's biggest outsourced chip packager and, by its own cited figures, the third-largest globally with about a 12.2% share of the outsourced packaging and test market. Its answer to TSMC's CoWoS is a homegrown platform called XDFOI (芯粒多维异构集成), and in 2025 it moved from pilot to volume.
Why packaging became the new frontier
Advanced packaging glues multiple chips — compute dies, I/O, and high-bandwidth memory (HBM) — into one system using silicon or organic interposers, through-silicon vias, and micro-bumps. When raw transistor scaling stalls, this "chiplet" approach delivers more bandwidth and efficiency per watt. It is exactly what AI accelerators need to keep feeding their compute.
JCET says XDFOI now supports 2.5D/3D integration with silicon interposer, silicon bridge, and organic RDL interposer paths, and has reached mass production of 4nm-class multi-chip integration. In co-packaged optics (CPO), it is integrating optical engines with switch or compute ASICs, and it has put a silicon-photonics engine sample into delivery.
The 2025 scale-up
JCET's 2025 results, released in 2026, show the push paying off:
- Total revenue of RMB 38.871 billion (≈ US$5.36B / HK$41.8B), a record.
- Advanced-packaging-related revenue of RMB 27.0 billion (≈ US$3.72B), also a record and roughly 70% of the business.
- R&D spend of RMB 2.086 billion (≈ US$287M), up 21.37%, part of a rise from RMB 1.19B in 2021 to about RMB 2.09B in 2025.
- A wafer-level micro-system project in Jiangsu — described as the largest single smart-manufacturing investment in China's packaging sector — completed phase one in 2025, adding high-end capacity.
The company also closed its acquisition of 80% of Sandisk's Shanghai packaging-and-test joint venture for about US$624M (≈ HK$4.87B), a deal announced in 2024 and fully paid by late 2025, folding in two decades of storage-packaging know-how and a foothold in enterprise SSDs.
Where the AI demand actually is
JCET points to three AI-linked engines. First, compute: its 2.5D platform serves domestic AI-chip designers building accelerators that need HBM attached. Second, memory: it cites progress on HBM3E packaging and test, and joint development of HBM4 thermal-compression-bonding processes. Third, power: a 2.5D vertical VCORE power module using system-in-package is in production, aimed at the dense power delivery AI racks require.
A new Lin-gang (临港) automotive-electronics plant began production in March 2026, extending the high-reliability manufacturing base beyond compute into cars.
The honest competitive picture
JCET is a packaging and test house, not a foundry. It does not make the leading-edge logic wafers or the HBM itself; it assembles what others fabricate. Its XDFOI is a credible CoWoS-class alternative, but TSMC's CoWoS capacity and yield lead remain substantial, and much AI volume is locked into foundry-captive supply chains. JCET's edge is autonomy and cost for the domestic accelerator ecosystem, plus capacity that Western OSATs (ASE, Amkor) also compete for as foundries outsource some 2.5D/3D work. For investors, the read is that packaging is where China's AI supply chain has the most defensible autonomy today, even as it remains dependent on foreign logic and memory wafers it does not yet make at the leading edge.
What readers can do now
- If you follow semiconductors, watch advanced-packaging revenue share as the real AI-exposure metric — it now exceeds two-thirds of JCET's business and signals where value is migrating.
- Track HBM packaging and CPO as the next capability checkpoints; a packager's ability to handle HBM3E/4 and optical engines determines its AI relevance.
- Separate "packaging leadership" from "foundry leadership." They are different layers; a strong packager is not a substitute for leading-edge wafer fabrication.
Honest limitations
Figures come from JCET's official 2025 results and disclosures, supplemented by Chinese financial-media and research-report commentary; the 12.2% global OSAT share and #3 ranking are company-cited and should be read against varying third-party tallies. The US$624M Sandisk stake price is taken from Shanghai Stock Exchange filings (the authoritative source), not the larger figures circulating in some trade media. Specific customer names and HBM joint-development partners are characterized generally because detailed commercial terms are not publicly itemized.
Key takeaways
- JCET (长电科技), China's largest packager and a cited global No.3 (~12.2% OSAT share), scaled its XDFOI 2.5D/3D platform to mass production of 4nm-class chiplets in 2025.
- 2025 revenue reached RMB 38.871B (≈ US$5.36B), with advanced packaging at RMB 27.0B (≈ US$3.72B, ~70% of sales); it closed an ~US$624M Sandisk Shanghai stake acquisition.
- Packaging is now the AI-value frontier as transistor scaling slows, but JCET assembles others' wafers and HBM rather than fabricating them — a different layer from a foundry.