A base-station engineer in Chengdu waits months for a programmable chip that, a few years ago, would have arrived in two. The delay is not a factory hiccup. It is a policy, and it has reshaped who supplies China's adaptable silicon.
Field-programmable gate arrays (FPGAs) are the chameleons of the chip world — rewired after manufacture for 5G, aerospace, industrial, and the messy inference jobs GPUs handle poorly. They are also a quiet front in the chip contest.
Key takeaways
- The two Western giants, AMD (Xilinx) and Intel (Altera), plus Lattice, hold about 90% of the global FPGA market; in China their combined share fell from 78% in 2021 to about 57% in 2025.
- Domestic vendors — Pango Micro (紫光同创), Fudan Micro (复旦微电), and Anlogic (安路科技) — reached a combined roughly 29% of China's market by 2025, per industry estimates.
- US export controls removed the civilian exemption for advanced FPGAs to China; lead times stretched from 8–12 weeks to roughly 52 weeks and prices rose 10–20%.
- Substitution has been fastest in low- and mid-density parts; high-capacity devices above about 500k logic cells remain an international stronghold.
- China has about 22 FPGA vendors and mainstream 28nm products, with 14/16nm parts in development.
The control that backfired into demand
The turning point was bureaucratic. US rules removed the civilian exemption that had let advanced FPGAs ship to China with minimal friction. AMD and Intel paused or reviewed large orders; lead times for imported parts extended from the usual 8–12 weeks to roughly 52 weeks, and Xilinx and Lattice raised prices 10–20% on key lines. For Chinese buyers, the message was clear: do not assume the part you designed around will be there.
That uncertainty became a market opening. Industry analyses (JW Insights and others) estimate that the combined China share of AMD and Intel fell from 78% in 2021 to about 57% by 2025, while the three leading domestic vendors climbed to roughly 29% together. Pango Micro is cited as the local leader, Fudan Micro as the broadest product line, and Anlogic as the volume leader in small- and mid-density parts, with cumulative shipments past 200 million units in that segment.
The ceiling is still high
The catch is where the substitution happened. Domestic FPGAs have won in military-spec, consumer, and industrial low-end roles, and are moving into communications and mid-range industrial. The high-capacity devices — above about 500k logic cells, the kind that compete with AMD's largest parts — remain where international vendors dominate. Anlogic's top Phoenix part reaches about 400k logic elements; AMD demonstrated 18-million-logic-cell devices years ago. Closing that gap is a matter of process node, tooling, and software, not just design talent.
China's vendors are pushing: Fudan Micro spans 50k to 40-million-gate logic and has taped out smaller-batch 1x-nanometre, billion-gate parts; Pango has FinFET Titan-3 parts and a 14nm, 100-million-gate product in development. But 28nm remains the mainstream domestic node, and 14/16nm is still in progress. The software toolchain — place-and-route, timing closure, and the mature IP libraries that surround a programmable device — lags the silicon, which is why even qualified mid-tier parts take time to displace imported ones in conservative designs.
Why this matters beyond the spec sheet
FPGAs are a stress test for adaptable compute — the kind needed when an AI workload is too fragmented for a GPU and too small to justify a custom ASIC. According to Li An, chief scientist at BrainNet (脑机网), China's FPGA gap is less about any single chip than about the design-tools and long qualification cycles that surround adaptable hardware, and those take longer to build than the devices themselves.
The export-control logic cuts both ways. Washington narrowed supply to slow China's high-end compute; China answered by building a domestic mid-tier that is now entrenched. The frontier it cannot yet reach is precisely the segment the controls targeted.
Honest limitations
Market-share figures (78%→57%, domestic ~29%) come from industry-research houses (JW Insights, cited across several trade reports) and vary by source; they are estimates, not audited market data. The lead-time and pricing effects are attributed to those same analyses and to US rule changes, not to a single primary disclosure. Domestic vendors' financials are partly A-share disclosed, but profitability differs sharply — Anlogic, for example, was not yet profitable on recent figures. I have not stated a separate global-market size because estimates for 2026 range from about US$9.7bn to US$13.6bn depending on the research firm.
What readers can do now
- Treat "FPGA国产化" as a low-end success and a high-end work-in-progress; the 29% share is real but concentrated below the capacity frontier.
- Watch for domestic 14/16nm FPGA tape-outs and design-tool progress — those, not shipment counts, signal whether the top tier is reachable.
- For procurement, assume long lead times on imported advanced FPGAs persist; qualify a domestic mid-tier part where the design allows, but budget for re-validation.