In the advanced packaging (先进封装) hall, the light is yellow and the air is filtered to a standard most factories never reach. A technician in a hooded suit carries a tray of substrates across the floor at a pace that looks unhurried and is not. On the wall beside the line, a screen shows yield by shift, and the numbers move in small increments.
The work here is not printing transistors. It is joining finished pieces: logic die to interposer, memory stack to logic, lid to package, package to board. Each join has a tolerance, each tolerance has a cost, and each cost lands on the price of the finished accelerator.
This is where China's chip plan is actually being tested. Not at the lithography tool, where the gap is well known, but two steps downstream of it.
Key takeaways
- Ascend 910C packages two 910B dies into one part with about 53 billion transistors and 128 GB of HBM.
- SMIC's N+2 7nm process yields around 40% without EUV, which sets the cost of every good logic die.
- Huawei targets 1.6 million Ascend dies in 2026, but memory supports only 250,000–400,000 packages, per a SemiAnalysis estimate.
- Domestic EDA tools are moving into production flows, but public adoption claims outrun published coverage and yield data.
- The binding constraint is engineering time — bonding, test and tool qualification — not the number of announcements.
Why the package became the product
For two decades packaging was a cost line: finish the wafer, send it to assembly, ship the part.
That changed when shrinking stopped paying for itself. Without access to EUV lithography, a Chinese fab cannot simply print a bigger monolithic die at the next node. It can, however, build a large system out of smaller dies that each fit inside the reticle limit, place them side by side on an interposer, and put memory stacks close enough to matter.
The approach has a name — the chiplet, assembled in a 2.5D package — and it converts a lithography problem into a packaging problem. That is a useful trade, because packaging tools are more widely available than EUV scanners. It is also expensive: every additional die is another chance to fail.
Four layers have to work together, and they fail independently:
- Logic die, which must yield well enough to be worth assembling.
- Memory, which must arrive in sufficient volume and at sufficient bandwidth.
- Packaging, which must bond, fill, test and cool the assembly.
- Tools, which must design and verify all of the above before a wafer is started.
A weakness in any layer caps the system, which is why the plan is best understood as a stack plan rather than a fab plan.
The 910C as a case study
The 910C is the clearest public example. It is not one die but two: a pair of 910B chips in a single package, together carrying about 53 billion transistors and 128 GB of HBM.
Two dies mean two yields multiplied together, two thermal sources, and a die-to-die link fast enough that software can treat the pair as one device. None of it is exotic; all of it is hard at volume, where difficulty is measured in dollars per good unit.
The design also explains Huawei's memory choices: if the package is the unit of assembly, memory is part of the product definition rather than an accessory bought later.
The tool gap
Behind the package sits software. Electronic design automation turns a specification into a layout, verifies it, and prepares it for manufacturing. It is a small market dominated by a handful of vendors, and substitution there is slowest.
Chinese toolmakers have made real progress, and domestic adoption is growing. The honest caveat is that public evidence is thinner than the announcements: coverage claims are common, published production data at advanced nodes is not.
Tool substitution is a habit rather than a purchase. Engineers qualify a flow over many tape-outs, and a flow that works at a mature node may not close timing at an advanced one. That curve cannot be compressed by procurement.
The yield math
SMIC's N+2 7nm process is reported to yield around 40% (SemiAnalysis). Set that against the die target: Huawei aims for 1.6 million Ascend dies in 2026, nearly triple the prior year.
Then set it against packaging. CXMT's 2026 output of roughly 2.2 million HBM stacks supports only 250,000–400,000 Ascend-class packages, according to the same analysis, while SMIC can make die for more than a million chips.
Two ratios follow. At 40% yield, most wafer starts do not become saleable die, so cost per good die stays high. And because memory caps finished units, some of that expensive die waits for stacks that do not exist. The constraints multiply.
A realistic timeline
The next public milestone in the sequence is the Ascend 960, scheduled for 2027. Beyond that, the order of work is predictable: memory volume first, because it caps packages today; packaging yield second, because it converts die into product; foundry yield third; tool maturity last.
Each step is measured in process generations and qualification cycles, not in launch events. That is why the useful signal is not a new announcement but a number: stacks per month, packages per month, yield by shift. The screen on the packaging hall wall is the story.
Honest limitations
Huawei does not publish packaging yields, package volumes or the split between domestic and imported memory. The 40% N+2 yield and the 250,000–400,000 package range are third-party estimates with wide error bars. Domestic EDA progress is documented mainly through company statements and industry reporting, not through independent benchmarks at advanced nodes. The 1.6 million die figure is a target. Everything about timing beyond 2027 is inference.
What readers can do now
- Operators: evaluate accelerators on packaged supply and support terms, not on announced die capacity that may never reach a board.
- Investors: treat packaging and memory as the gating assets in Chinese compute, and discount roadmaps that do not name a packaging partner.
- Researchers: when comparing Chinese accelerators, report the package configuration — die count, memory type, interconnect — because the same logic die behaves differently in different assemblies.