The tray holds a row of silicon towers, each a short stack of dies bonded face to face and wired through with microscopic channels. An engineer in a hairnet lifts one with tweezers, turns it against the light, and sets it down. The failure she is hunting is not in the silicon. It is in the join.
Stacking memory is a packaging problem before it is a chip problem. Every layer must be thinned, aligned, bonded and tested, and every layer multiplies the chance that a single bad join ruins the tower. It is the least photographed part of the supply chain, and it now sets the pace.
The logic die is no longer the scarce object. The memory sitting on top of it is.
Key takeaways
- CXMT's 2026 output of about 2.2 million high-bandwidth memory (高带宽内存, HBM) stacks supports only 250,000–400,000 Ascend-class packages, according to a SemiAnalysis estimate.
- SMIC can make logic die for more than a million Ascend-class chips, so memory and packaging — not lithography — cap the system.
- Huawei now specifies its own memory: 128 GB of HiBL 1.0 on the 950PR, 144 GB of HiZQ 2.0 on the 950DT.
- The 950DT carried a suggested price of about RMB 250,000 (≈ US$35,200 / HK$275,000) in September, up 60% in three months.
- Controls on advanced memory bite harder than controls on accelerators, because they cap the number of systems that can be assembled at all.
A stack is a yield problem in reverse
A logic die is one piece of silicon, tested once. A memory stack is eight or a dozen, each thinned, aligned to microns, bonded, filled and tested again as a unit. If one die in the tower is bad, the tower is scrap — and the good dies bonded to it go with it.
That inverts the usual economics. Normally you sort good die and discard the bad. Here you commit the whole tower before knowing whether it works.
Three things follow:
- Capacity is set by bonders, not by lithography tools.
- Yield losses compound, so cost per usable gigabyte stays high even when the process is mature.
- A single upstream supplier can cap an entire accelerator programme, however good the logic design is.
This is why the memory question is not a procurement detail. It is the ceiling.
The arithmetic of the bottleneck
CXMT's 2026 output of roughly 2.2 million HBM stacks, allocated to Ascend-class packages, supports somewhere between 250,000 and 400,000 units (SemiAnalysis). SMIC, by contrast, can produce logic die for more than a million such chips.
The gap between those two numbers is the story. China can print more brains than it can give them memory. Huawei's target of 1.6 million Ascend dies for 2026 is therefore not a shipment forecast; it is a statement about die capacity that runs well ahead of what can be packaged and sold.
The band is wide — a factor of 1.6 — and that difference separates a constrained market from a severely constrained one. Nobody outside CXMT and its customers knows where inside it the true figure sits.
Huawei's own memory
Huawei's response has been to stop treating memory as a commodity input and start specifying it. The 950PR ships with 128 GB of HiBL 1.0, a proprietary part. The 950DT carries 144 GB of HiZQ 2.0 at roughly 4.0 TB/s.
There is logic to proprietary memory when supply is constrained. If the standard part is unavailable, you design around what you can get and tune the interface to your own silicon. You also stop competing for allocation with every other buyer.
The cost is equally clear. Proprietary memory locks customers into one roadmap, complicates software tuning, and makes comparison with international parts harder to interpret. It solves a supply problem by creating a compatibility problem — a reasonable trade only when supply is the binding constraint.
Why the price keeps moving
The 950DT's suggested price rose to about RMB 250,000 (≈ US$35,200 / HK$275,000) per card in September, 60% higher than three months earlier. The 950PR moved from about RMB 60,000 to more than RMB 80,000, and the 910C from about RMB 90,000 to more than RMB 110,000.
Volumes are rising at the same time. In a healthy market that combination is impossible; prices fall as yields improve. Here it signals demand outrunning assembly capacity, and buyers bidding for units rather than negotiating.
Rotating chairman Xu Zhijun has said supply is short and priority goes to domestic demand — about as close to official confirmation as the company will give.
What it does to model design
Memory scarcity does not stay in the data centre. It propagates into how models are built and sold.
When memory is expensive relative to arithmetic, serving teams optimise for bytes moved rather than operations performed. Quantisation, cache reuse, mixture-of-experts routing and aggressive batching all become more valuable. The 128 GB and 144 GB configurations are not generosity; they specify a memory-bound workload.
The second-order effect is strategic: a lab that cannot assume abundant memory designs models that need less of it, and those models may be cheaper to serve anywhere. Constraint is a design teacher, though an expensive one.
Honest limitations
CXMT does not publish stack output, so the 2.2 million figure is an outside estimate, and the 250,000–400,000 package range is derived rather than disclosed. Huawei publishes capacity and bandwidth for its memory variants but not yields or prices paid. Advanced packaging yield is among the best-kept numbers in the industry, and none of the figures here come from an audited disclosure. Treat the direction as solid and the magnitudes as provisional.
What readers can do now
- Operators: ask for memory capacity, bandwidth and package lead time before you ask about peak throughput; the second number is meaningless if the first cannot be delivered.
- Investors: watch stack output and packaging capacity as leading indicators, and discount die-capacity announcements that are not matched by assembly lines.
- Researchers: report memory footprint and bandwidth per deployed model alongside parameter counts, because that is what determines whether a system can actually be served at scale.