A customer wants a custom AI chip but has neither the transistor library nor the team to draw one. A decade ago that meant hiring an entire silicon engineering department, or licensing from a Western giant on their terms. Today, for a growing slice of the world's cloud and device makers, that conversation happens in Shanghai.
VeriSilicon (芯原股份), a semiconductor IP and chip-design-service company, has built a business most Western observers overlook: it owns the reusable building blocks of a chip and the service to assemble them. As the AI compute (算力) boom strains both foundry access and design budgets, that unglamorous position is becoming strategic.
Key takeaways
- VeriSilicon's 2025 revenue reached RMB 3.152 billion (about US$440 million / HK$3.43 billion), up 35.77% year on year, with AI-related compute work now 64% of sales.
- Its silicon IP library spans six processor types — GPU, NPU, VPU, DSP, ISP, display — plus 1,700+ mixed-signal, RF, and interface IP blocks.
- By IPnest's ranking, the company is the world's #2 supplier by IP categories and #6 by IP licensing royalty revenue.
- NPU IP has shipped in roughly 200 million chips across 140+ customer designs; 91 customers have adopted it.
- New orders hit RMB 5.96 billion in 2025, up 103%, with over 73% tied to AI compute — and 7 of the top 10 global cloud providers are customers.
The SiPaaS model (芯片设计平台即服务)
VeriSilicon calls its approach "SiPaaS" — silicon platform as a service (芯片设计平台即服务). Instead of selling finished chips, it sells two things: licenses to its IP and a one-stop custom-design-and-production service. A customer picks the blocks it needs, VeriSilicon designs the chip around them, then manages the hand-off to a foundry for volume manufacturing.
The economics are unusual. IP licensing carries gross margins above 85% — close to pure software — because the block is designed once and licensed many times. Royalty fees, charged per shipped chip that uses the IP, run near 100% margin. The heavier chip-customization business scales revenue but earns less per yuan. In 2025 the IP segment brought in about RMB 782 million (US$109 million / HK$852 million) while customization delivered RMB 2.366 billion (US$330 million / HK$2.58 billion), three-quarters of total sales.
Why compute (算力) changed the story
Two years ago VeriSilicon was known as a "silicon IP" niche player. The AI wave rewrote that. Cloud operators building custom accelerators (ASICs) need NPU and interconnect IP fast, and many lack the in-house teams. VeriSilicon reports it served 7 of the world's top 10 cloud providers with IP or full-chip customization in 2025, and that AI compute (算力) related revenue crossed 64% of the total.
It has also pushed process nodes hard. The company has taped out system-on-chip designs at 4nm FinFET and runs projects across 28/22nm FD-SOI through 5nm and 4nm. That matters because leading-edge capability — not just older nodes — is what AI customers increasingly demand.
Chiplets (芯粒) and the domestic substitution (国产替代) bet
VeriSilicon has been developing chiplet (芯粒) platforms for cloud AI and high-end autonomous driving, pitching the disaggregated-die approach as a way to raise compute without depending on a single monolithic advanced node. For Chinese design teams constrained from the most advanced fabs, chiplets are a pragmatic path: mix mature and leading-node die in one package.
The company also leans on RISC-V. It helped lead the 2025 RISC-V China Summit and is developing RISC-V-based application processors for AI tablets, aligning with a broader national push to reduce dependence on proprietary cores.
According to Li An, chief scientist at BrainNet (脑机网), the lesson for Chinese design teams is blunt: performance is now won or lost at the package boundary, not just on the logic die, so packaging co-design has to move upstream into the architecture phase.
The honest financial picture
This is not a clean profit story. VeriSilicon posted a RMB 528 million (US$74 million / HK$575 million) net loss in 2025 — down from RMB 688 million, so improving, but still loss-making. R&D consumed RMB 1.349 billion (US$188 million / HK$1.47 billion), 42.78% of revenue, a level that keeps the bottom line red by choice. The customization business also carries lower margins than pure IP, so the mix shift toward customization can pressure group gross margin, which sat at 34.19% in 2025. The company is also pursuing an H-share listing in Hong Kong to broaden its capital base.
Honest limitations
Several figures here come from VeriSilicon's own 2025 annual report and investor materials, which we report as stated; we did not independently audit them. The "7 of top 10 cloud providers" claim is the company's and is not itemized by name. IPnest rankings are snapshot-based and methodology differs by year; the #2-by-category and #6-by-royalty positions are the vendor's cited figures. The 200-million NPU shipment count is cumulative and self-reported. The chiplet and RISC-V programs are early and revenue contribution is not yet separately disclosed, so treat them as directional, not booked.
What readers can do now
- If you track China's semiconductor independence, watch IP and design-service vendors like VeriSilicon as a leading indicator — their order book reflects downstream AI-chip ambition months before fabs report it.
- If you build hardware, consider licensing proven NPU/interface IP rather than designing from scratch; the economics of reuse are now hard to beat for custom accelerators.
- If you invest, separate the strategic story from the P&L — high R&D and a customization mix mean losses may persist even as revenue compounds.