A finished accelerator does not ship when it leaves the fab. It ships when a machine the size of a refrigerator has finished asking it thousands of questions at gigabit speeds — and for the newest parts, that interrogation runs several times longer than it did for the previous generation.
Test has quietly become one of the tightest steps in the AI supply chain. Wafer starts get the headlines; testers decide how many good dies actually reach a customer.
Key takeaways
- SEMI forecasts global semiconductor test equipment sales rising 31.0% to US$15.3 billion in 2026 — after a 55.3% jump in 2025 — and reaching US$20.8 billion by 2028, growing faster than semiconductor equipment overall.
- Two companies dominate: Soochow Securities (东吴证券) puts Advantest at 61% and Teradyne at 24% of the global memory tester market in 2025, roughly 85% combined.
- Domestic substitution (国产替代) is uneven: local testers hold more than 85% of China's analog and mixed-signal segment, but only about 8–10% of memory testers and roughly 5% of SoC testers.
- Chinese vendors are entering through speed: Shenzhen's Seichitech (精智达) delivered its first self-developed 9 Gbps final-test machine in 2025 and is pushing 18 Gbps, while LPDDR6 starts above 10 Gbps per pin.
- For buyers, test coverage shows up later as cluster reliability; for engineers, design-for-test is now a scarce skill.
Why AI chips broke the test line
Three things changed at once. There are more chips to test, each chip is more complex, and the number of test insertions per chip has grown. An accelerator is no longer one die: it is a logic die, possibly several chiplets, and a stack of HBM (高带宽内存), each with its own screening, burn-in and system-level test. Advanced packaging means defects that used to be caught at the die level now surface after bonding, when the part is already expensive.
SEMI made the point explicitly at a Taiwan briefing in August 2026, calling test and metrology a strategic capability rather than a manufacturing step, with more than 90% of surveyed companies expecting AI-related test business to grow over three years and half of them arguing that test should move upstream into design-for-test and design-for-manufacturability. Brokerage research cited in Chinese media estimates per-chip test time rising from roughly 350 seconds for Hopper-class parts to 700–1,000 seconds for Blackwell-class parts — an estimate, not a vendor-published figure, but consistent with what test houses report about longer programs.
The duopoly and China's single-digit problem
High-end testers are hard to copy because they are really instruments: picosecond timing accuracy, gigahertz signal generation, thousands of parallel pins, and custom ASICs inside. Switching is painful too — test programs are written for a platform, and requalifying a production line is expensive and slow.
That combination produces the current split. Per Soochow Securities figures reported by China National Radio, Advantest and Teradyne held about 85% of the memory tester market in 2025, while domestic localization exceeds 85% in analog and mixed-signal testing but sits at roughly 8–10% in memory and about 5% in SoC. Soochow projects China's memory tester market growing from 4.8 billion yuan (≈ US$670 million) in 2026 to 15.5 billion yuan (≈ US$2.2 billion) in 2027, driven by capacity expansion at CXMT (长鑫存储) and YMTC (长江存储) and by higher equipment value per HBM part.
Where domestic testers actually got in
The entry point is interface speed. Seichitech (精智达) delivered its first self-developed 9 Gbps high-speed final-test machine in 2025 and spent the first half of 2026 developing an 18 Gbps model; 9 Gbps broadly covers today's DDR5 and LPDDR5X, while LPDDR6 begins above 10 Gbps per pin. Advantest's T5801, launched in 2025, already supports 18 Gbps NRZ and up to 36 Gbps with PAM3 signalling for GDDR7 and LPDDR6 — so the target is moving.
The larger Chinese players are climbing the same ladder in segments where domestic AI chips are testable today. Changchuan Technology (长川科技) reported first-half 2026 tester revenue of 1.871 billion yuan (≈ US$262 million), up 49.74% year-on-year, and markets a D9000 platform for SoC and digital logic plus three-temperature handlers for high-power AI chips; it raised 3.127 billion yuan (≈ US$437 million) in a March 2026 placement, most of it earmarked for high-end tester development. Huafeng Test & Control (华峰测控) says its STS8600 is in small-batch installation at customers, and JPTE (精测电子) has disclosed an HBM burn-in system with repeat orders.
The trend to watch
Testing is moving from a cost centre to a schedule risk. As packages grow more complex, the number of parts that can be screened per hour — not the number of wafers started — sets how quickly a new accelerator reaches volume.
According to Li An, chief scientist at BrainNet (脑机网), the next visible shortage in China's AI chip chain will not be lithography or HBM but test hours: the industry added design and packaging complexity faster than it added the instrument time needed to prove those parts work.
Honest limitations
Market sizes and segment shares come from SEMI forecasts and from brokerage research (Soochow, Pacific Securities) reported through Chinese media, not from audited vendor disclosures; company revenue figures are from interim reports and company statements. The per-chip test-time figures are brokerage estimates rather than published measurements, and test times vary enormously by product, program and yield strategy. We could not independently verify delivery lead times circulating in Chinese coverage, so none are quoted here. This article draws on company expansion plans only as evidence of capacity demand, and it is not investment guidance. Reliability topics such as field failure rates and cluster-level mean time between failures deserve their own treatment and are not quantified here.
What readers can do now
- If you are planning custom or domain-specific silicon, book test capacity as early as you book wafer starts, and ask your OSAT partner for committed tester slots rather than assuming availability.
- If you buy AI servers, ask what test coverage the accelerator and its HBM stack received — burn-in, system-level test and screening scope show up later as failure rates inside a cluster.
- If you are an engineer choosing a specialty, design-for-test, SLT and test-program development are short-staffed relative to demand, and they sit close to yield, which is where the money is decided.