The memory inside an AI (人工智能) accelerator matters as much as the compute die next to it. Without enough bandwidth, even the fastest chip stalls waiting for data. That is why a single qualification decision in Seoul became a signal for the entire AI hardware cycle.
In early June 2026, NVIDIA chief executive Jensen Huang told reporters in Seoul that all three major memory makers — Samsung Electronics, SK hynix, and Micron Technology — had been qualified and were in production for high-bandwidth memory 4 (HBM4), the memory standard for NVIDIA's next-generation Vera Rubin AI platform. The first systems were slated to ship in the third quarter of 2026. Reuters and Bloomberg both reported the comments.
Key takeaways
- NVIDIA confirmed all three leading memory suppliers are qualified and in volume production for HBM4, with first Vera Rubin systems shipping in Q3 2026.
- HBM4 is a structural upgrade: the JEDEC JESD270-4 standard doubles the interface width to 2,048 bits and targets at least 2 terabytes per second of bandwidth per stack.
- SK hynix has begun shipping 12-layer HBM4 for NVIDIA and demonstrated a 12-layer HBM4E sample in June 2026, according to its own announcements.
- Vera Rubin succeeds the Blackwell platform and is built around agentic AI workloads that need far more memory bandwidth per query.
- Industry analysts estimate SK hynix will hold the largest HBM4 share, though NVIDIA has not published official allocation figures.
Why HBM4 is a structural break
HBM stacks DRAM dies vertically and connects them through tiny through-silicon vias, sitting next to the compute die on the same package. HBM4 changes the geometry: where HBM3E used a 1,024-bit interface, HBM4 moves to 2,048 bits with 32 independent channels, roughly doubling the baseline bandwidth per stack to at least 2 TB/s under the JEDEC floor. It also separates command and data buses to cut latency during the heavy multi-channel traffic of large-model training and inference.
This matters because modern large model (大模型) serving is memory-bound. A reasoning agent that runs hundreds of tool-use steps per prompt generates far more memory traffic than a simple chatbot reply. HBM4 is the component that lets Rubin-class systems keep those pipelines fed.
The three-supplier signal
Huang's statement ended months of speculation that HBM4 supply might be too tight to support a 2026 ramp. By naming all three suppliers as qualified and racing to support Vera Rubin, NVIDIA signaled a multi-source memory base rather than dependence on a single vendor. That reduces single-point supply risk and gives NVIDIA leverage in price negotiations.
SK hynix, long NVIDIA's key memory partner, has moved aggressively. The company announced it began shipping 12-layer HBM4 for NVIDIA and, in June 2026, shipped 12-layer HBM4E samples. It has also laid out a long-term capacity expansion targeting roughly a doubling of DRAM wafer capacity by the early 2030s, concentrated in its Yongin semiconductor cluster. Samsung and Micron are likewise in the race, with Micron reported to have started high-volume production of 12-high HBM4.
What it means for the AI build-out
More HBM4 supply at volume lowers the risk that memory — not logic — gates the next AI platform launch. It also reinforces South Korea's central role in the AI supply chain, since two of the three qualified suppliers are Korean. For model developers, steadier HBM supply means the next generation of accelerators should be available in larger quantities than the often-constrained Blackwell rollout.
The catch is cost and physical limits. HBM4 stacks must be thinned to roughly 50 micrometers per die, and 16-high stacks planned for a later "Rubin Ultra" class push that to about 30 micrometers while staying within package height limits. Those are hard manufacturing constraints that no qualification announcement removes.
The qualification also resets expectations for the Blackwell-to-Rubin handover. Where the prior transition was dogged by HBM3E shortages, Rubin enters with three qualified sources from day one, which both lowers single-point supply risk and strengthens NVIDIA's hand in price talks.
Honest limitations
The "all three qualified and in production" claim is attributed to NVIDIA's CEO and reported by Reuters and Bloomberg; specific per-vendor shipment volumes and market-share percentages (e.g., SK hynix share estimates) come from analyst reports and Korean media and were not independently verified. HBM4 bandwidth and interface figures reflect the JEDEC specification, not necessarily shipping product performance. Timeline statements (Q3 2026 ship) are NVIDIA's guidance and may slip.
What readers can do now
- Treat HBM4 as the gating component for the next AI accelerator generation; monitor supplier qualification news as a leading indicator of accelerator availability.
- If you plan AI infrastructure, assume Rubin-class systems become broadly available only as HBM4 volume scales through late 2026 and 2027.
- Watch SK hynix, Samsung, and Micron capacity announcements — memory, not logic, is the tighter constraint for the coming AI hardware cycle.