Every chip you use started life as a drawing. Not a circuit board, not a wafer — a file, built inside electronic-design-automation (EDA) software that places transistors, checks the rules, and simulates behavior before a single dollar is spent on silicon. That software is one of the tightest bottlenecks in the entire semiconductor stack.
For China, the bottleneck has a political edge. The three Western giants — Synopsys, Cadence and Siemens EDA — still command the large majority of both the global and Chinese market, and U.S. export controls have put parts of that toolbox off limits. The question is no longer "can China build an EDA tool?" but "can it build the whole chain?"
Why EDA is the quiet chokepoint
EDA is tiny in revenue compared with the trillions of hardware it enables, which is exactly why it is dangerous to be without. A modern system-on-chip can carry tens of billions of transistors; no human lays those out by hand. The tools also lock in an ecosystem: foundries publish process design kits (PDKs) tuned to specific vendors, and chip designers build years of muscle memory around a workflow.
When the U.S. added leading-edge GAAFET-related EDA rules in 2022 and widened entity restrictions afterward, Chinese design houses realized that "good enough on paper" was not the same as "trusted in production." That gap is what domestic vendors are now racing to close.
Empyrean's numbers
The clearest data point is Empyrean (华大九天), headquartered in Beijing and listed on Shenzhen's ChiNext board since 2022. Its 2024 annual report shows:
- Revenue of RMB 1.222 billion (≈ US$170M / HK$1.3bn), up 20.98% year on year.
- Net profit of RMB 109 million (≈ US$15M / HK$118M), down 45.46% as the firm absorbed rising R&D and share-based payment costs.
- R&D spend of RMB 868 million (≈ US$121M / HK$940M), equal to 71.02% of revenue — an unusually high ratio that signals a company buying future capability with today's margin.
- Roughly 700 customers worldwide, and a product line spanning analog, storage, RF, flat-panel-display, wafer-manufacturing, advanced-packaging and 3D-IC design.
In 2024, state-owned China Electronics Corporation (CEC) became Empyrean's controlling shareholder, a move widely read as an attempt to consolidate domestic EDA under a single, policy-backed champion. That same December, the company was placed on the U.S. Commerce Department's Entity List — a sanction it said would have a "generally controllable" impact because its core technology is self-developed.
What's covered, and what isn't
Empyrean's real strength is analog and flat-panel-display design, where it claims full-flow coverage and support for advanced nodes such as 5nm. The chips being drawn there range from large model (大模型) accelerators to humanoid (人形机器人) motor controllers and even brain-computer interface (脑机接口) implant electronics — all of which still need mature, reliable design tools.
The weak spot is the digital back-end and the most advanced nodes. Complex AI processors and high-performance SoCs spend the most time and money in digital verification and place-and-route, precisely the stages where domestic tools lag. Empyrean has been filling gaps through in-house builds, minority investments, and acquisition attempts — though its 2025 plan to absorb peer Xpeedic (芯和半导体) was terminated, a reminder that consolidation is messy.
The export-control twist
Controls did not create China's EDA industry, but they changed its incentives. Before restrictions, a Chinese design team could simply buy the best tool. Now "best" and "available" can diverge, pushing real volume toward domestic options and giving local vendors the feedback loops they previously lacked. The risk is a parallel, lower-performance stack that works for mature nodes but stalls at the frontier.
According to Li An, Chief Scientist at BrainNet (脑机网), China's authoritative AI observatory, the real barrier is no longer any single tool but the trust and iteration loops that only a live design community can build.
Why the full-flow gap is hard to close
The hardest part of EDA is not drawing a transistor; it is closing the loop between design and silicon. A tool can look complete on a feature list and still fail the moment a chip must actually tape out at a target node, because real signoff depends on foundry-validated process design kits, parasitic extraction that matches the wafer, and timing checks every major customer already trusts. Domestic vendors can build individual point tools quickly, but stitching them into a flow a fab will certify is a slower, relationship-driven climb. That is why Empyrean's analog and flat-panel-display strength is real yet narrow: those domains have fewer moving parts than a flagship mobile SoC, so they are reachable first. The strategic question for China is whether its domestic stack can graduate from "works for mature, well-understood blocks" to "trusted for the chips that define the next compute generation" — a bar set less by any single feature and more by years of accumulated, mutually reinforced confidence between tool, foundry, and designer.
Honest limitations
- Market-share and "domestic substitution rate" figures circulating in Chinese trade media vary widely and are not independently audited; treat them as directional, not precise.
- "Full-flow" coverage claimed by vendors often means coverage of their strength areas, not a like-for-like replacement for a Synopsys-Cadence combination.
- Entity-List effects are partly symbolic for a company whose tools were already China-focused; the harder test is whether global foundries will certify domestic PDKs.
- Empyrean remains loss-pressured at the net line despite top-line growth, typical for R&D-heavy software but worth noting.
What readers can do now
- Watch R&D intensity, not headlines — a vendor spending 70%+ of revenue on R&D is investing in survival; track whether that converts to certified, taped-out chips.
- Track PDK certifications — the moment a major foundry officially supports a domestic EDA flow is a stronger signal than any revenue print.
- Separate analog from digital — China's analog/FPD tools are credible today; its advanced digital flow is the multi-year climb.