For five weeks in mid-2025, the software that designs nearly every advanced chip in the world stopped flowing to China. Then it started again. The episode was short, but it showed exactly where the pressure points of the semiconductor war sit — not in the factories, but in the design tools.
Electronic design automation, or EDA, is the unglamorous software layer beneath the entire chip industry. No leading-edge silicon gets built without it. And three companies — Synopsys, Cadence and Siemens EDA — control more than 90% of the global market and over 70% of China's, according to Chinese commerce-ministry-linked reporting.
Five weeks that reset the toolchain
On May 29, 2025, the US Commerce Department's Bureau of Industry and Security (BIS) told Synopsys, Cadence and Siemens EDA that they needed a license to sell chip-design software to China. The three complied, and Chinese design teams briefly lost access to parts of the tools they use daily.
The reversal came almost as fast. On July 2–3, BIS notified the companies the restriction was lifted, effective immediately. Synopsys said it was restoring access to the recently limited products; Siemens said Chinese customers had full access again; Cadence confirmed the same through Reuters. The whole episode lasted about five weeks.
Short as it was, the blackout was a stress test. It confirmed that China's chip-design industry runs on foreign EDA for the hardest problems, and that a single policy letter in Washington can freeze that dependency overnight. That is precisely why Beijing has treated EDA autonomy as a strategic priority for years.
What EDA actually is
Think of EDA as the compiler-plus-blueprint engine for silicon. It takes a chip description and handles logic synthesis, placement and routing, timing and power analysis, and sign-off verification before a single wafer is etched. For the most advanced nodes it is a stack of hundreds of tightly integrated tools. The three Western giants sell "full-flow" suites that cover the whole path; almost everyone else sells point tools that do one job well.
That concentration is the vulnerability. When the tools are foreign, every Chinese chip design — military or consumer, AI accelerator or washing-machine controller — ultimately depends on software whose export can be switched off.
Huawei's head start above 14nm
China did not start from zero. In March 2023, Huawei's rotating chairman Xu Zhijun (徐直军) said the company, working with domestic partners, had localized the EDA tools needed for processes above 14 nanometers and would finish full verification that year. The claim came from Huawei's own "software and hardware tools" rally, where it said it had replaced 78 development tools across hardware, software and chip lines to keep R&D running after US sanctions cut off updates.
"Above 14nm" is the key caveat. It covers a huge share of real-world chips — automotive, industrial, power, many AI inference parts — but not the leading-edge logic where EUV-built nodes live. Still, it meant that for a broad slice of Chinese chip design, a domestic tool path already existed before the 2025 shock.
The home-grown toolbox takes shape
The domestic EDA field is led by Empyrean (华大九天), often described as China's only vendor with both analog and digital full-flow ambitions. Industry reports say its analog platform supports 28nm and below, with 14nm FinFET tape-out verification, and that its ALPS+ digital backend platform has closed the layout-to-sign-off loop validated at SMIC's 28nm and 14nm processes. Empyrean's customers are reported to include SMIC, Huawei, YMTC and CXMT.
Alongside it, Primarius (概伦电子) built a strong position in device modeling: its BSIM and SPICE tools are reported to be incorporated into the PDKs of TSMC and Samsung — a rare "reverse certification" where foreign foundries trust a Chinese tool for process modeling. Other names, such as X-EPIC (芯华章) in verification and UniVista (合见工软) in hardware emulation, fill gaps in the digital flow.
The honest verdict from engineers is that domestic EDA has moved from "can it work?" to "is it good enough for this node?" — usable at mature and 14nm-class processes, still maturing at the very leading edge. The 2025 blackout did not create that capability, but it removed any doubt about why it matters.
What readers can do now
- Treat EDA as a leading indicator of chip sovereignty: watch which Chinese fabs certify domestic tools at which node, not just product launch headlines.
- For design teams, pilot a domestic EDA point tool on a mature-node project now, while access to Western suites is restored — the next blackout may not be five weeks.
- Follow Empyrean and Primarius earnings and PDK certifications as the clearest public signal of substitution progress.
Honest limitations
The May–July 2025 BIS restriction and its lifting are confirmed by Synopsys, Siemens and Cadence statements reported via Reuters and Chinese state-linked media. The "90% global / 70% China" market-share figures come from Chinese commerce-ministry-linked reporting and are widely cited but rounded. Huawei's 14nm-and-above EDA localization is a company statement from 2023, not an independently benchmarked claim, and explicitly excludes leading-edge nodes. Empyrean's and Primarius's node and customer specifics come from industry trade reports rather than primary filings, and should be treated as indicative. None of this is investment advice.