Everyone watching the AI hardware race talks about the compute chip — the accelerator doing the math.
Almost nobody talks about the memory stacked next to it, which the accelerator is useless without.
That quiet component, high-bandwidth memory (高带宽内存, HBM), is where China just put its first visible marker.
Key takeaways
- CXMT (长鑫存储, ChangXin Memory Technologies), China's largest DRAM maker, began supplying HBM3 samples to domestic customers including Huawei in 2025, reportedly several months ahead of its own schedule.
- The samples are built on CXMT's DDR5 base using a 16nm "G4" process, with an 8-die stack; the vertical bonding step is outsourced to packaging specialists.
- HBM is the bottleneck memory for AI accelerators, and today more than 90% of it comes from Samsung, SK hynix, and Micron.
- CXMT's roadmap targets HBM3 mass production in 2026 and HBM3E by 2027, with dedicated HBM capacity planned at roughly 50,000 wafers per month.
- The move matters because US export controls have made advanced HBM hard for Chinese chip designers to buy, turning domestic supply from nice-to-have into strategic.
Why HBM is the story hiding inside the AI chip
An AI accelerator is only as fast as the memory feeding it. High-bandwidth memory (高带宽内存, HBM) is the stacked, tightly-coupled DRAM that sits beside the compute die; without enough of it at high bandwidth, even a powerful chip stalls. For the largest models, HBM is a hard constraint on both training and inference.
Until recently, that market was an oligopoly. Samsung, SK hynix, and Micron together supply well over 90% of global HBM. For Chinese accelerator designers — Huawei's Ascend (昇腾) line, Cambricon's 思元 (Siyuan) parts, and others — access to the newest HBM has been squeezed by US export controls that treat advanced memory as a controlled item. That is the gap CXMT is now trying to fill.
What CXMT actually did in 2025
CXMT is China's largest DRAM manufacturer, founded in Hefei in 2016 and run as an IDM — it designs, fabricates, and packages its own memory rather than only designing it. Long focused on commodity DRAM, the company spent years climbing the ladder from older nodes toward DDR5.
In 2025, Korean and Chinese industry reporting indicated CXMT began delivering initial HBM3 samples to key domestic customers, with Huawei named as the first recipient. Coverage described the samples as arriving roughly four months ahead of the company's earlier public timeline. The parts are reported to integrate CXMT's own DDR5 dies using a proprietary "G4" process at a 16nm node, with eight DRAM layers stacked vertically. The sensitive vertical-stacking and thermal-compression bonding steps are described as outsourced to outsourced semiconductor assembly and test (OSAT) partners — the same division of labor the big three memory makers use.
These are sample shipments, not mass production, and the reporting is from industry and Korean media rather than a CXMT press release. The credible read is that China has moved from "no domestic HBM" to "early HBM3 samples in customer hands" — a real milestone, but several steps behind the established suppliers.
The roadmap, and its limits
The same reporting lays out CXMT's stated path: deliver HBM3 samples through 2025, move to volume production in 2026, and target the next generation, HBM3E, around 2027. The company has been described as aiming for dedicated HBM capacity on the order of 50,000 wafers per month, a fraction of what the Korean leaders run but enough to seed domestic supply.
Two limits are worth stating plainly. First, CXMT's reported HBM3 still trails the leading edge — the big three are already shipping HBM3E and sampling HBM4, so a multi-year gap remains in process and stacking maturity. Second, the most advanced packaging steps are not yet done in-house, which matters because TSV (through-silicon via) and bonding are precisely the capabilities export controls target. Still, the direction is clear: a fourth name is entering a market that was a comfortable trio.
The bigger chessboard
CXMT's HBM push sits inside a wider shift. The company built scale first in commodity DDR4, where aggressive pricing pushed the established memory makers to retreat from the low end and concentrate on high-margin HBM. By entering HBM, CXMT is now threatening the one segment those rivals had reserved as their fortress. Industry observers in South Korea have openly compared the dynamic to how Chinese competition reshaped the LCD panel market.
Capital is following the strategy. Chinese media reported in mid-2026 that CXMT's public listing drew roughly RMB 58 billion (about US$8 billion / HK$63 billion) in subscriptions, described as the largest on the STAR Market to that point — a signal of how seriously the market treats domestic memory autonomy.
For global readers, the point is not that China has caught the memory leaders. It is that the AI supply chain's most controlled component is now being reproduced domestically, which changes the calculus of export control: the harder the outside supply is squeezed, the stronger the incentive to build the inside one.
Honest limitations
The central claim — CXMT shipping HBM3 samples to Huawei in 2025 — comes from Korean and Chinese industry media (including reporting attributed to Korea's Financial News), not from a CXMT or Huawei official announcement, and should be read as well-sourced industry reporting rather than confirmed corporate disclosure. Specific process details (16nm "G4," 8-die stack, 50,000 wafers-per-month HBM capacity) are likewise from secondary coverage and may shift. The IPO subscription figure is from Chinese media and is presented as reported. This article focuses on HBM and DRAM; it does not cover CXMT's NAND sibling Yangtze Memory (长江存储), its legacy DRAM pricing strategy in depth, or the separate question of whether domestic HBM will clear the quality and yield bar for frontier AI training at scale.
What readers can do now
- Treat "HBM sample shipped" as a starting line, not a finish: track CXMT's move from samples to qualified, volume HBM3 in 2026 as the real test of domestic AI memory.
- Watch the advanced-packaging supply chain (TSV and bonding OSAT capacity inside China) — that, not the DRAM wafer, is the controlled chokepoint for HBM.
- When assessing Chinese AI compute claims, ask which HBM they assume; a powerful accelerator with no secured advanced memory is a spec sheet, not a deployed system.