The smallest transistors are no longer the whole story. As chips hit physical limits, the way dies are stacked and connected has become a battleground of its own — and China is spending heavily to win it.
A sudden wave of spending
Advanced packaging — the art of connecting and enclosing finished chips — used to be the unglamorous end of the semiconductor business. That changed when AI accelerators started needing stacks of high-bandwidth memory bolted next to a computing die. Suddenly the package, not just the transistor, set the performance ceiling.
The spending confirms it. TrendForce reported in July 2026 that nearly ten major advanced-packaging projects were announced across China between May and July alone, with total disclosed investment approaching RMB 40 billion (≈ US$5.6bn / HK$44bn).
The anchor deal came from JCET (江苏长电科技), one of the world's largest outsourced packaging and test providers. On 24 June 2026 it announced a high-end advanced-packaging plant in Shanghai's Lingang area, with total investment of RMB 7.8 billion (≈ US$1.1bn / HK$8.6bn), built in two phases and aimed at high-density redistribution layers, ultra-fine-pitch bumping, large-format heterogeneous integration, and chiplet multi-die packaging for AI servers and high-performance computing. Phase I is scheduled to enter production in the second half of 2028.
Two days later, Forehope Electronic (甬矽电子) unveiled a RMB 10.3 billion (≈ US$1.45bn / HK$11.3bn) packaging base in Yuyao to be built over eight years. On 13 July, a Union Semiconductor (合封半导体) subsidiary launched a "HITS" advanced-packaging project in Shanghai with investment of at least RMB 7.5 billion (≈ US$1.06bn / HK$8.25bn).
Why packaging matters more now
The logic is architectural. A modern AI chip's power depends as much on how many layers of memory can be stacked on top of it as on raw transistor density. Taiwan's TSMC popularised the CoWoS process that does exactly this; everyone building AI silicon now queues for it. When the most advanced lithography is restricted, stacking becomes the practical lever to add performance without a smaller transistor.
For China, the race for compute (算力) is now as much about packaging as about silicon. Chiplets — mixing dies built on different process nodes into one package — let designers reserve scarce advanced-node capacity for the parts that need it, and use mature nodes for the rest.
The strategic logic for Beijing
Packaging is also the softer target. Export controls have focused on lithography and high-end manufacturing tools, not on the assembly and test steps. That means Chinese firms can scale packaging with equipment that is easier to source domestically, and they can practice the craft on automotive and consumer chips while climbing toward AI-grade work.
The South China Morning Post quoted JCET's Zheng Li arguing that the industry's focus has shifted "from how to increase the number of transistors per unit area to how to improve the quality of the chip." That single sentence captures the pivot.
The hard parts nobody tweets about
Packaging a multi-die part is not easier than making the die. A package can become as difficult as the silicon itself: die-to-die links must be high-bandwidth and low-latency, thermal management gets harder as layers stack, and the yield of the final package depends on every component being known-good.
There are material gaps too. Advanced packages increasingly need glass or specialty substrates, and some of those upstream inputs are still imported. Equipment maturity for ultra-fine bonding and high-density redistribution layers is improving but not yet at the volume and reliability of the most established foreign lines.
Memory packaging joins the race
The buildout is not only about logic and AI compute. TrendForce notes that memory packaging is also drawing capital: Huatian Technology is expanding a Nanjing advanced-memory packaging site with about RMB 3 billion (≈ US$0.42bn / HK$3.3bn), while Biwin Storage launched a roughly RMB 1 billion (≈ US$0.14bn / HK$1.1bn) AI-memory packaging project in the Greater Bay Area. The motive is the same as for logic — as AI systems hit the "memory wall," packing memory closer to the processor becomes a performance lever. For China, memory packaging is doubly attractive because it depends less on the restricted lithography stack and more on integration know-how it can practice at scale.
Honest limitations
- The RMB 40 billion total and individual project figures are disclosed investment intentions reported by TrendForce and Pandaily, not completed or qualified capacity.
- The marquee JCET plant's Phase I timeline runs to the second half of 2028, so none of this is near-term supply.
- China still trails TSMC's CoWoS in both volume and production maturity for the highest-end AI packages.
- Several key substrates and bonding tools remain partly import-dependent, which caps how fast the buildout converts into yield.
What readers can do now
- Read JCET, Tongfu and Huatian order books and utilization as a demand signal for AI and automotive chips, not just foundry utilization.
- Track TSMC's CoWoS supply and pricing — it sets the global ceiling that Chinese packaging is trying to fill.
- Qualify domestic advanced-packaging partners early if you build hardware; the real constraint will be yield and throughput, not press announcements.