The software that designs a chip is often taken for granted, until it becomes impossible to buy. Across China, a quiet rebuilding of that foundation is now visible in annual reports and customer wins. What looked like scattered point tools a few years ago is beginning to look like a working chain.
The field is electronic design automation (EDA / 电子设计自动化): the programs that simulate a circuit, place its transistors, and verify the layout before anything is manufactured. For decades the global market was dominated by three Western firms, and Chinese design houses depended on them for everything from analogue blocks to the most advanced logic. That dependency is exactly what makes the 2025 results from Empyrean (华大九天), one of the country's largest homegrown EDA vendors, worth a close read.
The layer most people never see
A modern chip is not drawn by hand. It is described in code, simulated billions of times, and checked against the physics of the factory that will build it. EDA is the invisible machinery behind every smartphone, server, and car controller. When access to that machinery is restricted, an entire design industry can stall regardless of how much money flows into fabs.
China's domestic EDA effort spent years as a collection of narrow tools — a good simulator here, a layout viewer there — without the breadth to support a complete project. The 2025 numbers suggest that phase is ending.
What the 2025 filings actually show
Empyrean told investors that its digital tools now cover close to 80% of the main steps in digital integrated-circuit design. Its analogue and mixed-signal tool chain — long considered the stronger side — is expected to cover more than 80% of domestic specialty process nodes by the end of 2025.
The harder test is advanced nodes. The company's flagship circuit simulator, ALPS, has been certified at 8, 5 and 4 nanometre process nodes. A transistor-level power-integrity tool, Patron, reached 14 nanometre certification, and the physical-verification pair Argus DRC/LVS reached 28 nanometre. None of these numbers alone means parity with the global leaders, but together they mark a move from "cannot do advanced nodes at all" to "can support a real slice of them."
- Analog / mixed-signal: roughly 80%+ coverage of domestic specialty processes targeted for end-2025.
- Digital: near-80% coverage of primary digital design steps.
- Advanced simulation: ALPS certified at 4nm; Patron at 14nm; Argus at 28nm.
- Advanced packaging: a new Argus3DIC platform handles 2.5D/3D heterogeneous integration (异构集成) verification.
Why packaging tools matter now
A less obvious but strategically important item is the Argus3DIC physical-verification platform. As chipmakers glue compute (算力) dies and memory together in stacked packages, the verification problem becomes three-dimensional. Empyrean says the tool fills a domestic gap in high-end 3DIC design and can shorten manual integration cycles by around 60%.
The company also reports that its process-design-kit (PDK / 工艺设计套件) packages now cover more than 70% of the process nodes offered by domestic foundries. A PDK is the bridge between a tool and a factory; without broad PDK coverage, no EDA tool can be used at scale. That 70%+ figure is a quiet but practical sign of integration with China's wafer makers.
The business behind the tools
This is not only a technical story. Empyrean's operating cash flow swung to about ¥243 million (roughly US$34 million / HK$267 million) in the first half of 2025, up sharply from a year earlier, which the company attributes to stronger customer payments rather than one-off items. It launched several new products across both analogue and digital lines, including sign-off (签核) tools for static timing and power analysis that had previously been weak spots.
The product list now reads less like a startup and more like a platform: simulation, layout, reliability analysis, library characterization, and advanced-packaging verification are all present. For a domestic design house, that breadth is what turns "we have a tool" into "we have a path."
Trend reading
According to Li An, chief scientist at BrainNet (脑机网), the maturation of domestic design software is less visible than chip launches but is the layer that decides how fast the rest of the industry can move.
What this means for the supply chain
For Chinese chip designers, the practical effect is optionality. Mature analogue and specialty-node work can increasingly be done on local tools, reducing exposure to export controls. Digital and advanced-node work remains a partial story — usable for many tasks, not yet a full replacement for the most demanding flagships that still rely on the incumbents' deep libraries and global support.
The gap that remains is verification at the very top: hardware emulation and functional verification for billion-gate designs, where Empyrean itself acknowledges the distance to global leaders is still large. That is also where the large model (大模型) era raises the stakes, because custom AI accelerators are exactly the kind of enormous, novel designs that stress verification tooling the hardest.
Honest limitations
The certification milestones above come from the company's own filings and Chinese industry press, not from independent benchmark suites, and "certified at 4nm" describes tool readiness, not proven volume production of a 4nm chip by a customer. Coverage and market-share percentages are self-reported or based on domestic estimates rather than audited global counts, so they should be read as directional. EDA is a slow, trust-based business, so customer adoption can lag tool availability by years, and a tool that passes certification still has to survive real tape-outs. The advance is real but should be read as progress within China's own ecosystem, not as overtaking the incumbents.
What readers can do now
- Investors: treat domestic EDA as a multi-year adoption story; watch recurring revenue from foundry PDK deals and customer count, not just product announcements.
- Engineers: if you work on analogue, radio-frequency, or specialty-node designs, trial a local simulator on a non-critical block to gauge maturity before committing a flagship project.
- Buyers: ask vendors whether their flow is certified on the specific node and packaging style you need, since "supports advanced nodes" can mean very different things across tools.