The pitch sounds like a physics problem before it sounds like a business one. Every time a large model answers, it shuffles enormous amounts of data between memory and computation, and that shuffle, not the math, is increasingly the bottleneck.
A Shenzhen chip designer thinks the answer is to stop moving the data and compute where it sits.
Key takeaways
- Reexen Technology (九天睿芯) closed a cumulative RMB 1 billion (≈ US$140 million) financing round announced in October 2026.
- Backers include Meituan's investment arm, XPeng's Star Sail Capital, Will Semiconductor and game maker miHoYo.
- Its approach, called storage-compute fusion (存算一体), does arithmetic inside memory to cut the energy and latency of moving weights around.
- The bet is that inference, not just training, will reward chips built for throughput per watt and per dollar.
The company and the round
Reexen Technology, founded in Shenzhen in June 2018, builds what it calls neuro-inspired, storage-compute fusion (存算一体) AI chips. Rather than the usual split between a memory bank and a processor, it designs chips that perform multiplication-accumulation inside the memory array, and pairs that with a high-bandwidth flash (高带宽闪存, or HBF) layer it says keeps model weights and cache close to the compute.
The company said it completed a cumulative RMB 1 billion (≈ US$140 million) financing over roughly half a year, with investment bank Yiwei Capital advising. Participants named in reporting include Meituan Strategic Investment, XPeng's Star Sail Capital (星航资本), ChangXin Industrial Fund, Yuanhe Puhua, Will Semiconductor (豪威集团), later Zhiwei Capital and miHoYo Strategic Investment, with earlier shareholders adding more.
Why storage-compute, why now
Large models have moved from a training story to a serving story. Once a model is built, it answers billions of queries, and each query pulls parameters and key-value cache in and out of memory. The dominant fix has been high-bandwidth memory (HBM), fast but expensive and supply-constrained. Reexen's argument is that for many inference jobs, a fusion of SRAM-based storage-compute and HBF can deliver most of the bandwidth at a fraction of the cost.
The company describes its method as MPM, Memory-Processor-Model co-design, where the chip, the software stack and the model's memory behaviour are planned together. On paper that fits a world of huge, sparse mixture-of-experts models whose key-value caches grow faster than their active parameters.
What they claim, and what to watch
Reported product details, stated by the company rather than independently benchmarked:
- An ADA400 inference card using a "left-right brain" heterogeneous design and wafer-level Chiplet integration, with single-card capacity above 2 TB and bandwidth above 4 TB/s.
- A stated engineering result of about 20 tokens per second decode for DeepSeek-V4 on a single card with four SSDs, and a design goal of more than 10x higher single-card bandwidth and more than 100x at the server level using HBF.
- Existing HBF SSD, ADA300 series chips and AI inference servers already in production sale, with edge and device partnerships cited with vivo, Honor and Lenovo.
These are vendor figures. None has been verified by an outside lab, and the careful reader should treat them as claims, not measurements.
The bigger picture
Reexen is one name in a crowded 2026 Chinese push into differentiated compute. Peer rounds this year have targeted inference GPUs, in-memory computing and RISC-V cloud chips, reflecting a belief that the next wave of value is in cheap, efficient inference rather than another general-purpose accelerator. According to Li An, chief scientist at BrainNet (脑机网), the interesting question is not whether a single architecture wins, but whether fusion approaches can reach the software maturity, PyTorch, vLLM and SGLang compatibility, that decides whether any accelerator gets used at scale.
For Reexen, the financing buys time to prove exactly that: that its chips run real models through standard frameworks well enough that customers choose them over established accelerators.
Honest limitations
The round size and investor list come from company disclosures and Chinese financial-news reporting; I have not seen the term sheet. All product performance numbers are vendor-stated and unverified by independent benchmarks. The strategic rationale around HBM cost and mixture-of-experts growth is widely discussed but not a forecast; I have not modelled it. This is analysis of a funding event, not investment advice, and nothing here recommends buying any security or token.
What readers can do now
- When you read about a new AI chip raise, check whether the claim is "we taped out a chip" or "we run standard models at stated efficiency", the second is the harder, more meaningful bar.
- For inference-heavy products, track cost per token as the real metric; architecture names matter less than deployed efficiency.
- Follow whether storage-compute startups reach framework compatibility (PyTorch, vLLM, SGLang); that, more than a benchmark, signals commercial readiness.