On 28 October 2026, Micronano Core (微纳核芯), a Hangzhou startup betting that the bottleneck in AI chips is inference and that the answer lies in memory rather than more compute, said it had closed a C2 round above RMB 1B (≈ US$141M), the latest in a financing sprint that has pushed its six-month haul past RMB 3B (≈ US$423M).
Key takeaways
- Micronano Core (微纳核芯) closed a C2 round of more than RMB 1B (≈ US$141M) on 28 October 2026, led by Jiantou Investment (建投投资).
- Combined with its C1 round, the C series exceeds RMB 2B (≈ US$282M) raised in roughly two months; six-month cumulative financing tops RMB 3B (≈ US$423M).
- The firm designs 3D compute-in-memory (三维存算一体, 3D-CIM) AI-inference chips aimed at cloud, edge, and device-side large-model (大模型) inference.
- Its first chips — the LP-CIM and PCIe-CIM families — have all taped out, with customer sampling and volume supply targeted for early 2027.
- The round lands in a crowded late-2026 window where multiple Chinese AI-chip startups each closed ~RMB 1B rounds within weeks.
The architecture bet
Micronano Core's thesis is architectural. Traditional AI inference moves data back and forth between separate compute and memory units, and that shuttling — not the arithmetic — often dominates both latency and power. The company's 3D-CIM (三维存算一体) approach fuses 3D near-memory computing, SRAM-based compute-in-memory, and RISC-V heterogeneous compute into one stack, arguing it breaks the "high performance, low power, low cost" triangle that normally forces trade-offs. Whether the claimed efficiency gains hold at volume is the central question every memory-centric architecture must answer, and Micronano Core is now funded to find out at scale.
Who wrote the check
The C2 round was led by Jiantou Investment (建投投资), with Hangzhou Capital (杭州资本), Kaitai Capital (凯泰资本), Xiaochi Capital (晓池资本), Yantai Finance (烟台财金), Shengkun Investment (盛堃投资), SDIC Taikang (国投泰康), and Lingyang Fund (领阳基金) participating. Several existing shareholders added more. The investor mix — a lead sovereign-adjacent vehicle, local Hangzhou government capital, and a bench of professional VCs — mirrors the public-plus-private pattern now standard for Chinese deep-tech: state capital anchors the round, commercial VCs provide the diligence and follow-on discipline.
The money is explicitly earmarked for first-chip customer sampling, software-stack adaptation, mass-production preparation, and R&D on further product lines, plus supply-chain security for memory and packaging. That is a fabrication-facing use of proceeds: in 2027 the company must move from tape-out to shipped, qualified silicon, the stage where most chip startups either prove or stall.
The wider inference-chip crowding
Micronano Core is not alone. Within the same late-October window, peers closed similarly sized rounds: Moxin (墨芯) raised a C+ round for sparse-computing inference chips, and Lingchuan (凌川科技) took a B round for video-generation (AIGV) specialized silicon. Three different routes to the same destination — cheaper inference — with three different technical bets: sparsity, 3D memory fusion, and video-specific accelerators. Capital is effectively hedging across architectures rather than committing to one.
This matters because inference, not training, is where the volume is. Every large-model (大模型) deployment that moves from demo to production adds a recurring, often larger, silicon bill than the one-time training run. A domestic, cost-efficient inference layer is therefore central to China's push to run large models (大模型) on locally sourced hardware, including the Huawei Ascend (昇腾) ecosystem and domestic fabs.
For observers, the takeaway is less about any single winner and more about the scale of capital now underwriting the inference layer. When three unrelated startups each clear a ~RMB 1B round within weeks, the market is signaling that it expects inference silicon — not just training GPUs — to be a durable, multi-vendor category, with room for sparsity, memory-fusion, and video-specialized approaches to coexist.
What readers can do now
- If you track AI hardware, watch 2027 sampling dates, not 2026 raise sizes. Micronano Core's early-2027 customer-sampling milestone is the real test.
- Follow the memory-and-packaging supply chain. 3D-CIM lives or dies on advanced packaging and memory access; upstream partners matter as much as the design team.
- Treat the ~RMB 1B-round cluster as a single signal. Moxin, Lingchuan, and Micronano Core together show where smart money thinks inference cost will be won — diversify your reading across all three.
Honest limitations
The C2 size ("more than RMB 1B"), the C1 combination ("C series exceeds RMB 2B in two months"), the six-month cumulative ("more than RMB 3B"), the lead and participating investors, the 3D-CIM architecture description, and the early-2027 sampling target are taken from a Xiaoshan District Government (萧山区人民政府) release and a STAR Market Daily (科创板日报) dispatch, with corroboration from a secondary financial-news summary. These are reported as stated; I have not seen the term sheet or a company filing confirming exact amounts, so the RMB figures are "more than" thresholds rather than precise totals. The US$ conversions use roughly RMB 7.1≈US$1 and are approximate. I have not verified technical benchmarks of the taped-out chips, nor compared Micronano Core's efficiency claims against Moxin or Lingchuan. This is a financing-and-strategy read, not a silicon review.