--- title: "SMIC stretches DUV lithography to 7nm and eyes 5nm without EUV" date: 2026-10-27 category: Chips & Compute site: NeuroAI canonical: https://neuroai.site/a/na-smic-7nm-duv-foundry-ai language: en --- # SMIC stretches DUV lithography to 7nm and eyes 5nm without EUV > China's largest foundry is mass-producing 7nm-class chips with only DUV tools, becoming the bottleneck — and the backbone — of domestic AI compute. The most important machine missing from SMIC's (中芯国际) clean rooms is the one it cannot buy. Yet the wafers keep coming, and so do the AI accelerators built on them. China's largest foundry (代工) has become the single tightest constraint on the country's ambition to build its own computing power — and the clearest proof that advanced chips can be made without the West's crown-jewel tool. ## Key takeaways - SMIC is the only mainland Chinese foundry (代工) volume-producing a 7nm-class node (N+2) — achieved with deep-ultraviolet (DUV) lithography (光刻) and multi-patterning, not EUV. - The N+2 process is in stable mass production with reported yields above 80%; a 5nm-class node (N+3) entered risk production in late 2025. - Semianalysis estimates conservative advanced-node capacity of 45,000 wafers/month by end-2025, rising to 60,000 in 2026 and 80,000 in 2027. - SMIC's market capitalization crossed RMB 1 trillion in September 2025; its Q3 2026 guidance points to 2–4% sequential revenue growth and 26–28% gross margin. ## The constraint everyone watches Every Huawei Ascend, every Cambricon Siyuan, every domestic AI accelerator eventually lands on a SMIC wafer. That makes the foundry the throat of China's compute-supply chain. The catch: the most advanced node SMIC can run relies on DUV scanners doing the work EUV was invented for, repeating exposure steps four times to print finer lines — a technique called quadruple patterning. It works, but it is expensive and yield-hungry. Each extra patterning pass multiplies defect risk and tool time. That is why SMIC's advanced output, while real, stays a fraction of what TSMC ships on EUV at the same node. ## What is actually in production By SMIC's own and analyst accounts, the node map looks like this: - **N+2 (7nm-class):** stable mass production, 12-inch wafers, roughly 35,000 wafers/month capacity and reported yields above 80%, already used for flagship phone SoCs and AI accelerators. - **N+3 (5nm-class):** entered risk production in late 2025 and small-batch trial in 2026 — the first EUV-free 5nm-class solution claimed anywhere, though volume and yield remain unproven. - **14nm FinFET:** mature mass production at yields above 95%, a steady revenue pillar. - **28nm and above:** more than 75% of total capacity, yields above 95%, serving auto, IoT, and industrial demand. The strategy is explicitly two-track: flood mature nodes for cash while grinding advanced nodes upward one yield point at a time. ## Capacity math that matters Semianalysis' conservative tally puts SMIC's advanced (7nm-and-below) capacity at 45,000 wafers per month by end-2025, 60,000 in 2026, and 80,000 in 2027. Industry estimates cited in Chinese securities research place 2026 domestic AI-chip demand for sub-7nm wafers at roughly 150,000–200,000 wafers for the year, with SMIC filling a large share. Huawei is also building its own fabs through a tool-making arm, SiCarrier, and collaborating with SMIC on process technology — a move that could lift overall domestic advanced capacity beyond the single-foundry ceiling. None of that is export-controlled across the board, but none of it closes the EUV gap either. ## The financial backdrop SMIC listed on the STAR Market in July 2020, raising a then-record RMB 53.23 billion (about US$7.5 billion / HK$58 billion). In September 2025 its share price hit RMB 127.49 (about US$18) and its market capitalization surpassed RMB 1 trillion (about US$141 billion). In May 2026 a RMB 40.6 billion (about US$5.7 billion / HK$44 billion) merger cleared to give SMIC full control of SMIC North (中芯北方), a 12-inch mature-node plant above 70,000 wafers/month. Utilization ran in the low-to-mid 90 percent range through 2025 and the first half of 2026, and Q3 2026 guidance called for revenue up 2–4% sequentially at 26–28% gross margin — healthy, but with depreciation from aggressive capex a persistent drag. ## Why this matters beyond China SMIC is the stress test for a thesis Washington and Beijing both doubted: that meaningful advanced silicon can be built without EUV. The answer so far is "yes, but smaller, costlier, and slower." For global readers, that means export controls slow Chinese compute, they do not stop it — and they push innovation toward packaging, architecture, and DUV process tricks rather than a straight node race. ## Honest limitations Yield and capacity figures for N+2 and N+3 are analyst and media estimates, not SMIC audited disclosures of advanced-node specifics — the company does not break out advanced-node yield publicly. "5nm-class" via DUV is widely reported but remains at risk-production stage; commercial volume and cost are unproven. Depreciation pressure, entity-list restrictions on equipment, and cyclical demand swings all cap how fast the ceiling rises. SMIC is not TSMC, and the gap in the most advanced nodes is real. ## What readers can do now - Track SMIC's reported utilization and capex guidance each quarter — they are the cleanest public proxy for advanced-node stress. - Watch whether N+3 moves from risk production to named commercial chips; that is the real 5nm test. - Follow Huawei's SiCarrier fab build-out, since added domestic capacity, not just SMIC's, will define 2027 supply. --- Published by NeuroAI (https://neuroai.site/) — https://neuroai.site/a/na-smic-7nm-duv-foundry-ai Free to quote with attribution and a link to the original.